SpaceX

1 month ago

Sr. ASIC DFT Engineer (Silicon)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Develop and optimize design-for-test (DFT) architectures for next-generation SpaceX ASICs, integrating DFT IPs, running ATPG, and enabling efficient post-silicon bringup. Collaborate with cross-functional teams to ensure DFT features meet production requirements, leveraging Siemens Tessent tools and scripting to analyze data and automate test processes. This role supports Starlink-scale space and ground infrastructure testing across advanced node technologies.

Location: Sunnyvale

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

•Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools
•Integration and verification of Design for Test (DFT) IPs and fabrics within Subsystems
•Set up and run Automatic Test Pattern Generation (ATPG) tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows
•Run and debug non-timing and SDF annotated gate-level simulations
•Create and validate DFT patterns for post-silicon bringup and also help with ATE debug through all cycles of silicon characterization

Pay and Benefits

Salary: USD 135,000 - 185,000 annually

Equity and Bonus:Equity

Key Requirements

•Bachelor’s degree in electrical engineering, computer engineering, or physics. 5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing.
•Master’s or PhD in electrical engineering, computer engineering, physics, or related engineering field.
•Extensive experience in post-silicon bringup, including silicon debug, failure analysis, and yield optimization on complex SoCs or ASICs.
•Hands-on experience with Automated Test Equipment (ATE) platforms (e.g., Teradyne, Advantest) for high-volume manufacturing test development and debug.
•Experience collaborating with cross-functional teams to ensure DFT features meet production requirements, utilizing Siemens Tessent workflows.

Experience:5+ yearsSemiconductorDFTASICSoC

Education:Bachelor's

Skills:Problem-solvingCommunicationTeam collaboration

Languages:English

Tech Stack:PerlPythonTclC++Siemens TessentATPGIEEE 1500IEEE 1687IEEE 1149.1TeradyneAdvantestSDFPost-silicon bringup

Company Brief

SpaceX

Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.

Industry: Aerospace Manufacturing

Company Size: Enterprise (1,001+ employees)

Growth: Established Company

Valuation: Hectocorn (USD 100B+)

Funding: Series E+

Headquarters: Hawthorne, United States

Founded: 2002

Glassdoor: 4.2

Website LinkedIn

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SpaceX

1 month ago

Sr. ASIC DFT Engineer (Silicon)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Location: Sunnyvale

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

•Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools
•Integration and verification of Design for Test (DFT) IPs and fabrics within Subsystems
•Set up and run Automatic Test Pattern Generation (ATPG) tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows
•Run and debug non-timing and SDF annotated gate-level simulations
•Create and validate DFT patterns for post-silicon bringup and also help with ATE debug through all cycles of silicon characterization

Pay and Benefits

Salary: USD 135,000 - 185,000 annually

Equity and Bonus:Equity

Key Requirements

•Bachelor’s degree in electrical engineering, computer engineering, or physics. 5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing.
•Master’s or PhD in electrical engineering, computer engineering, physics, or related engineering field.
•Extensive experience in post-silicon bringup, including silicon debug, failure analysis, and yield optimization on complex SoCs or ASICs.
•Hands-on experience with Automated Test Equipment (ATE) platforms (e.g., Teradyne, Advantest) for high-volume manufacturing test development and debug.
•Experience collaborating with cross-functional teams to ensure DFT features meet production requirements, utilizing Siemens Tessent workflows.

Experience:5+ yearsSemiconductorDFTASICSoC

Education:Bachelor's

Skills:Problem-solvingCommunicationTeam collaboration

Languages:English

Tech Stack:PerlPythonTclC++Siemens TessentATPGIEEE 1500IEEE 1687IEEE 1149.1TeradyneAdvantestSDFPost-silicon bringup

Company Brief

SpaceX

Industry: Aerospace Manufacturing

Company Size: Enterprise (1,001+ employees)

Growth: Established Company

Valuation: Hectocorn (USD 100B+)

Funding: Series E+

Headquarters: Hawthorne, United States

Founded: 2002

Glassdoor: 4.2

Website LinkedIn