RTL Design Engineer

AMD
United States
Workplace: OnsiteFull timeUSD 126,700 - 217,200 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Communication","Teamwork","Analytical skills","Problem-solving","Ownership"]

Own top-level RTL design and integration of AMD mixed-signal power management IP, driving it through timing closure and tape-out in partnership with physical design and verification teams. Serve as the primary interface between RTL and timing closure, develop and review SDC constraints, support signoff, and drive ECO/tape-out readiness. Collaborate across Analog, Firmware, Systems Engineering, and Architecture, including analog behavioral model bring-up, post-silicon correlation, and design reviews/mentoring.

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FursaFursa
AMD
AMD
1 day ago

RTL Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 11 hours agoStatus: Live

Job Summary

Own top-level RTL design and integration of AMD mixed-signal power management IP, driving it through timing closure and tape-out in partnership with physical design and verification teams. Serve as the primary interface between RTL and timing closure, develop and review SDC constraints, support signoff, and drive ECO/tape-out readiness. Collaborate across Analog, Firmware, Systems Engineering, and Architecture, including analog behavioral model bring-up, post-silicon correlation, and design reviews/mentoring.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Own top-level RTL design and analog macro integration for mixed-signal power management ICs and drive integration through tape-out.
  • •Partner with analog macro teams on block integration, including bring-up and debug of analog behavioral models in digital simulation.
  • •Act as primary interface between RTL design and physical design/timing closure; create/review timing constraints (SDC) and manage clock-domain crossings.
  • •Drive timing closure and ECO support through tape-out; own RTL signoff before each release to physical design (lint, CDC/RDC, synthesis QoR, connectivity checks).
  • •Collaborate with verification and cross-functional teams on test plans, bring-up/debug, and post-silicon silicon-to-RTL correlation; mentor junior engineers and lead design reviews.

Pay and Benefits

Salary: USD 126,700 - 217,200 annually

Key Requirements

  • •Own top-level RTL design and analog macro integration for mixed-signal power management ICs through tape-out.
  • •Experience writing and executing timing constraints (SDC) and driving timing closure on production silicon.
  • •Proficiency with synthesis, lint, and CDC/RDC tools and their integration into a design flow.
  • •Strong scripting skills in Python and TCL.
  • •Integration and debug of analog behavioral models (Verilog-AMS, real-number/wreal) in a digital simulation environment, including post-silicon bring-up and silicon-to-RTL correlation.
Education:Bachelor's in electrical/computer engineering
Skills:CommunicationTeamworkAnalytical skillsProblem-solvingOwnership
Languages:En-us
Tech Stack:SystemVerilogRTLSDCTiming closureTape-outSynthesisLintCDC/RDCPythonTCLVerilog-AMSReal-numberWrealUPFI2CSPIAPBSVID/PMBusUPF-based power intentConnectivity checks

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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