Director, Silicon Design Engineering

Lead physical design timing engineering for Intel’s next-generation System-on-Chip (SoC) products. Drive timing analysis and optimization, generate and validate timing constraints, and resolve timing violations across chip and block levels. Set PVT conditions, manage timing rollups, and develop high-quality timing models and methodologies. Collaborate with clocking, architecture, and logic design teams to maintain clock balance, optimize power delivery and partitioning, and advance SoC clocking flows for high-performance, low-power integration.