Intel

1 day ago

IP RTL Senior Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 32 minutes agoStatus: Live

Job Summary

Develop and validate IP logic for Unified Intel Chassis designs, partnering with architects to define protocol bridges and implement secure access control across multiple request paths. Own parity/ECC generation and error/fault behavior, build observability via logging/interrupt/error harvesting, and design telemetry for fabric health. Integrate debug and trace data paths, counters, status snapshots, and firmware-visible CSRs, supporting post-silicon correlation and root-cause analysis.

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Develop IP block logic designs, RTL coding, and simulations for functional units and subsystems.
•Define IP architecture and microarchitecture features and optimize RTL for power, performance, area, and timing.
•Implement secure MMIO access control and privilege-based filtering across AXI-Lite, APB, IOSF-SB, and HBW request paths.
•Design and validate parity/ECC and transaction error handling, including fault behavior for unauthorized access and corrupted transactions.
•Build observability flows (logging, interrupts, error harvesting) and telemetry/debug data paths for bring-up, stress triage, and post-silicon correlation.

Key Requirements

•8+ years of experience in logic design and RTL development.
•Bachelor's degree in electrical engineering, computer engineering, or a related field.
•Proficiency in Verilog and SystemVerilog for RTL coding and simulation.
•Strong understanding of digital design principles including timing analysis, power optimization, and area trade-offs.
•Experience with EDA tools for design and simulation (e.g., Synopsys, Cadence, Mentor Graphics) and IP integration workflows in SoC designs.

Experience:8+ years

Education:Bachelor's

Skills:CommunicationCollaborationContinuous learning

Tech Stack:VerilogSystem VerilogAXIAXI-LiteAPBIOSF-SBUVMSynopsysCadenceMentor GraphicsParity/ECCTelemetryRAS

Company Brief

Intel

Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor

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Intel

1 day ago

IP RTL Senior Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 32 minutes agoStatus: Live

Job Summary

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Develop IP block logic designs, RTL coding, and simulations for functional units and subsystems.
•Define IP architecture and microarchitecture features and optimize RTL for power, performance, area, and timing.
•Implement secure MMIO access control and privilege-based filtering across AXI-Lite, APB, IOSF-SB, and HBW request paths.
•Design and validate parity/ECC and transaction error handling, including fault behavior for unauthorized access and corrupted transactions.
•Build observability flows (logging, interrupts, error harvesting) and telemetry/debug data paths for bring-up, stress triage, and post-silicon correlation.

Key Requirements

•8+ years of experience in logic design and RTL development.
•Bachelor's degree in electrical engineering, computer engineering, or a related field.
•Proficiency in Verilog and SystemVerilog for RTL coding and simulation.
•Strong understanding of digital design principles including timing analysis, power optimization, and area trade-offs.
•Experience with EDA tools for design and simulation (e.g., Synopsys, Cadence, Mentor Graphics) and IP integration workflows in SoC designs.

Experience:8+ years

Education:Bachelor's

Skills:CommunicationCollaborationContinuous learning

Tech Stack:VerilogSystem VerilogAXIAXI-LiteAPBIOSF-SBUVMSynopsysCadenceMentor GraphicsParity/ECCTelemetryRAS

Company Brief

Intel

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor