SoC Digital Verification Engineer, Multimedia Lab

Design and verify video codec SoC hardware for large-scale FPGA/ASIC platforms. Own verification planning, build UVM-based reusable testbenches and verification components, and execute constrained-random and directed tests to reach 100% functional and code coverage. Perform gate-level and SDF timing simulation, support FPGA prototyping and hardware/software co-debugging on emulation platforms, and improve regression automation to boost verification efficiency and compute utilization.