Sr. Logic Design Engineer

Develop and optimize RTL logic for an IP block, including register transfer level (RTL) coding and simulation. Help define architecture and microarchitecture features, run quality checks across RTL and timing/power convergence, and apply strategies to meet power, performance, area, and timing goals. Review verification plans, resolve failing RTL tests, and ensure correct design features for Intel’s UCIE PHY IP for datacenter/server designs.