Staff DFT Engineer

Broadcom
India
Workplace: OnsiteFull timeFunction: QA, Test & Release EngineeringSkills: ["Collaboration","Problem-solving","Attention to detail"]

Own design-for-test (DFT) strategy and requirements for mixed-signal ICs, covering scan insertion, compression, ATPG, memory BIST, and JTAG. Lead DFT verification across gate-level and timing simulations, troubleshoot DFT issues (coverage, simulation failures, DRC improvements), and collaborate with design, STA, and layout teams to implement DFT logic correctly. Support silicon debug and ATE pattern delivery, using Mentor DfT tools, Synopsys DC/simulators, Primetime, and RTL/scripting skills.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Broadcom
Broadcom
2 days ago

Staff DFT Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 9 hours agoStatus: Live

Job Summary

Own design-for-test (DFT) strategy and requirements for mixed-signal ICs, covering scan insertion, compression, ATPG, memory BIST, and JTAG. Lead DFT verification across gate-level and timing simulations, troubleshoot DFT issues (coverage, simulation failures, DRC improvements), and collaborate with design, STA, and layout teams to implement DFT logic correctly. Support silicon debug and ATE pattern delivery, using Mentor DfT tools, Synopsys DC/simulators, Primetime, and RTL/scripting skills.
Location: India
Workplace: Onsite
Employment Type: Full time
Job Function: QA, Test & Release Engineering
Seniority: Mid level

Key Responsibilities

  • •Define DfT strategy and requirement specifications for mixed-signal IC designs.
  • •Perform DfT verification using gate-level and timing simulations, including IJTAG/SSN/ATPG validation.
  • •Troubleshoot DFT issues such as simulation failures, ATPG coverage gaps, and DRC improvements.
  • •Collaborate with design teams, STA engineers, and layout engineers to implement DFT logic and timing constraints for DfT modes.
  • •Support test engineering during silicon debug and ATE pattern delivery, including RTL coding and scripting to aid delivery.

Key Requirements

  • •Strong IC-level expertise in scan insertion, compression, ATPG, Memory BIST, and JTAG for mixed-signal designs.
  • •Expertise in IJTAG, SSN, and ATPG verification, including handling DFT verification coverage and simulation failures.
  • •Experience with Mentor DfT tools and Synopsys DC and simulator tools to define DfT strategy and requirement specifications.
  • •Hands-on ability to solve DFT problems, improve ATPG coverage and DRC, and define timing constraints for DfT modes with STA/Primetime.
  • •Experience supporting silicon debug and ATE pattern delivery, with RTL coding and shell/Perl scripting knowledge.
Skills:CollaborationProblem-solvingAttention to detail
Tech Stack:JTAGScan InsertionCompressionATPGMemory BISTIJTAGSSNMentor DfT toolsSynopsys DCPrimetimeGate-level simulationTiming simulationDFTRTL codingShell scriptingPerl scriptingSystemVerilog InterfacesLint checksATEDRC

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn