Lead Software Engineer

Cadence Design Systems
Noida
Workplace: OnsiteFull timeFunction: Software EngineeringExperience: 3-6 yearsEducation: bachelorsSkills: ["Verilog","Vhdl","Systemverilog","Uvm","C++","Hardware verification","SoC verification","Hvl","Pcie","Usb4","Mipi","Nvme"]

Lead Software Engineer role focusing on advanced HDL-based verification and debugging of complex digital systems (SoC) using SystemVerilog, C++, and HVL. You’ll work with HDL languages (Verilog/VHDL), SystemVerilog, and UVM to design and implement functional verification environments, leverage EDA tools, and automate processes, contributing to Cadence’s verification and design workflows in Noida.

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FursaFursa
Cadence Design Systems
Cadence Design Systems
7 months ago

Lead Software Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 9 hours agoStatus: Live
Reposted: similar role first listed 8 months ago

Job Summary

Lead Software Engineer role focusing on advanced HDL-based verification and debugging of complex digital systems (SoC) using SystemVerilog, C++, and HVL. You’ll work with HDL languages (Verilog/VHDL), SystemVerilog, and UVM to design and implement functional verification environments, leverage EDA tools, and automate processes, contributing to Cadence’s verification and design workflows in Noida.
Location: Noida
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering
Seniority: Sr. Manager level

Key Responsibilities

  • •Lead the design and implementation of functional verification environments for complex digital systems (SoC)
  • •Conduct simulation/emulation using HDL languages and debug design/verification issues
  • •Automate verification processes through scripting and tooling
  • •Work with SystemVerilog, C++, and HVL (SystemVerilog) to achieve robust verification coverage
  • •Collaborate across functions and geographies to ensure customer success in verification outcomes

Key Requirements

  • •3 to 6 years of relevant experience
  • •B. Tech/BE/M.Tech/ME degree
  • •Very good understanding of HDLs (Verilog/VHDL)
  • •Experience with SystemVerilog, C++, UVM
  • •Experience with Functional Verification of complex digital systems (SoC verification) using a Hardware Verification Language (HVL) like SystemVerilog
Experience:3-6 yearsSemiconductorEDASoC verificationHDLVerification environments
Education:Bachelor's
Skills:VerilogVhdlSystemverilogUvmC++Hardware verificationSoC verificationHvlPcieUsb4MipiNvme
Languages:English
Tech Stack:VerilogVHDLSystemVerilogUVMC++EDA toolsCadence

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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