Software Engineer II: Hardware Verification Compiler

Cadence Design Systems
Belo Horizonte
Workplace: OnsiteFull timeFunction: Software EngineeringExperience: 3+ yearsEducation: mastersSkills: ["Maintainable code","Performance improvement","Cross-team collaboration","Object-oriented programming","Data structures and algorithms","Formal verification awareness"]

Develop and maintain a high-quality C/C++ HDL compiler and runtime support for hardware-assisted verification solutions. Build a SystemVerilog compiler front-end, improve compiler performance and flows, and gain exposure to RTL simulation/synthesis and runtime environments. Work with cross-geo teams in Belo Horizonte to enhance products that support verification platforms such as Palladium and Protium.

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Cadence Design Systems
Cadence Design Systems
4 days ago

Software Engineer II: Hardware Verification Compiler

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Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live

Job Summary

Develop and maintain a high-quality C/C++ HDL compiler and runtime support for hardware-assisted verification solutions. Build a SystemVerilog compiler front-end, improve compiler performance and flows, and gain exposure to RTL simulation/synthesis and runtime environments. Work with cross-geo teams in Belo Horizonte to enhance products that support verification platforms such as Palladium and Protium.
Location: Belo Horizonte
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering
Seniority: Mid level

Key Responsibilities

  • •Develop maintainable, high-quality C/C++ code for an HDL language-based compiler and runtime support.
  • •Build the HDL compiler front-end for System Verilog.
  • •Improve compiler performance, infrastructure, and verification flows.
  • •Gain exposure to RTL simulation/synthesis and runtime environment.
  • •Collaborate with cross-geography teams to contribute to product enhancement.

Key Requirements

  • •Complete Bachelor's degree in computer science or computer engineering (or related) with 3+ years of experience.
  • •Complete Master’s degree in computer science or computer engineering (or related).
  • •Work experience with C/C++ programming language.
  • •Knowledge and expertise in compilers, including compiler front-end development.
  • •Experience with Unix environment and solid data structures and algorithms knowledge.
Experience:3+ years
Education:Master's in computer science or computer engineering (or related fields)
Skills:Maintainable codePerformance improvementCross-team collaborationObject-oriented programmingData structures and algorithmsFormal verification awareness
Languages:EnglishPortuguese
Tech Stack:CC++System VerilogVerilogVHDLHDLUnixTclPythonRTL simulationSynthesisCompilersObject-oriented programming

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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