Sr IP/CPU RTL Design Lead - CPU Team

AMD
Bengaluru
Workplace: HybridFull timeINR 4,860,800 - 6,944,000 annuallyFunction: Design (Product/UX/UI/Visual)Education: mastersSkills: ["Communication","Analytical thinking","Problem-solving","Leadership","Teamwork"]

Lead RTL design for AMD x86-core ISA and processor IP, covering clock/reset/power, IP integration, and subsystem-level architecture. Architect and optimize power management, cache, and coherency features using low-power RTL techniques and resolve inter-IP integration issues. Own clock-domain crossing and linting, partner with DFT/physical design/SoC teams, and deliver and document RTL features while mentoring junior RTL engineers.

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FursaFursa
AMD
AMD
19 hours ago

Sr IP/CPU RTL Design Lead - CPU Team

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Last checked: 1 hour agoStatus: Live

Job Summary

Lead RTL design for AMD x86-core ISA and processor IP, covering clock/reset/power, IP integration, and subsystem-level architecture. Architect and optimize power management, cache, and coherency features using low-power RTL techniques and resolve inter-IP integration issues. Own clock-domain crossing and linting, partner with DFT/physical design/SoC teams, and deliver and document RTL features while mentoring junior RTL engineers.
Location: Bengaluru
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Manager level

Key Responsibilities

  • •Drive RTL design for high-performance x86-core ISA features and clock/reset/power, including IP integration and subsystem-level design.
  • •Architect and design power management features, cache, and coherency, optimizing for power-efficient IP using low-power RTL techniques.
  • •Own clock-domain crossing and linting aspects across the IP and subsystem.
  • •Collaborate with DFT, Physical Design, and SoC teams to incorporate interdisciplinary feedback into RTL design.
  • •Lead RTL deliverables across the design team and mentor junior engineers while documenting design features.

Pay and Benefits

Salary: INR 4,860,800 - 6,944,000 annually

Key Requirements

  • •12+ years of experience in Digital IP/ASIC design and Verilog RTL development.
  • •Experience across the full IP design cycle, including requirements definition, architecture, and microarchitecture specification.
  • •Well-versed in RTL design verification, design quality checks, synthesis, timing closure, and post-silicon validation.
  • •Expert in Verilog RTL and multiscale digital IP/ASIC projects.
  • •Proficiency with front-end EDA tool sign-off flows; low-power design knowledge and Python/Perl scripting are pluses.
Experience:ASICDigital designX86Semiconductors
Education:Master's in Electrical/Electronics Engineering, Computer Engineering, or VLSI design Engineering
Skills:CommunicationAnalytical thinkingProblem-solvingLeadershipTeamwork
Languages:English
Tech Stack:RTLVerilogASICX86Clock/reset/powerDFTPhysical DesignSoCEDA toolsLow powerPythonPerlLinting

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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