Staff Digital Physical Implementation and Integration Engineer

Micron Technology
San Jose, California
Workplace: OnsiteFull timeUSD 145,000 - 246,000 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 5+ yearsEducation: bachelorsSkills: ["Debugging","Cross-group communication","Automation","Mentorship","Innovation"]

Own digital physical implementation and top-level integration for NAND designs, driving blocks and full-chip partitions from synthesis handoff through floorplan, placement, routing, and closure. Lead hierarchical design planning, partition creation, pin optimization, repeater/feedthrough insertion, and top-level assembly using LEF/DEF/GDS and constraint handoffs. Perform modeling, simulation, STA/DRC/LVS/EM/IR verification, debug cross-flow correlation issues, and automate/extend flows with Tcl/SKILL/Python.

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Micron Technology
Micron Technology
2 weeks ago

Staff Digital Physical Implementation and Integration Engineer

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Last checked: 5 hours agoStatus: Live

Job Summary

Own digital physical implementation and top-level integration for NAND designs, driving blocks and full-chip partitions from synthesis handoff through floorplan, placement, routing, and closure. Lead hierarchical design planning, partition creation, pin optimization, repeater/feedthrough insertion, and top-level assembly using LEF/DEF/GDS and constraint handoffs. Perform modeling, simulation, STA/DRC/LVS/EM/IR verification, debug cross-flow correlation issues, and automate/extend flows with Tcl/SKILL/Python.
Location: San Jose, California
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Drive physical implementation and top-level integration of large digital designs in NAND products, including synthesis handoff through floorplan, place-and-route, and closure.
  • •Own hierarchical design planning and top-level assembly: partition creation, pin optimization, repeater/feedthrough insertion, and integration of LEF/DEF/GDS/ETM/ILM outputs.
  • •Lead verification and sign-off: STA across corners plus DRC, LVS, and EM/IR, and iterate ECOs to convergence while correlating synthesis vs. APR vs. STA.
  • •Contribute to new product opportunities by supporting design layout, optimization of Memory/Logic/Analog circuits, and parasitic modeling for validation and tape-out revisions.
  • •Automate and improve methodologies by building flows in Tcl/SKILL/Python, extending internal make-based flow, and collaborating with STA/DFT/CAD/custom-layout teams.

Pay and Benefits

Salary: USD 145,000 - 246,000 annually
Perks:Health InsuranceDentalVisionPaid LeavePaid HolidaysParental Leave

Key Requirements

  • •5+ years of digital physical design with at least one full tapeout owned end-to-end.
  • •Bachelor’s degree in Computer Engineering or Electrical Engineering.
  • •Strong static timing analysis and debug skills, fluent with PrimeTime across MMMC and OCV/AOCV/POCV.
  • •Hands-on top-level digital integration experience driving a full-chip or large-partition design from planning through assembly and hand-off.
  • •Experience with Cadence Innovus Hierarchical Flow or Synopsys ICC2 Design Planning, plus physical verification with Calibre (DRC/LVS/antenna/PERC).
Experience:5+ yearsSemiconductorMemoryNANDDigital physical designEDASoC
Education:Bachelor's in Computer Engineering or Electrical Engineering
Skills:DebuggingCross-group communicationAutomationMentorshipInnovation
Tech Stack:Cadence InnovusSynopsys ICC2PrimeTimeCalibreTclSKILLPythonPerlLinux/UnixGitMakeSDCMMMCOCVAOCVPOCVLEFDEFGDSETM

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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