SpaceX

1 month ago

Sr. ASIC DFT Engineer (Silicon)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Senior ASIC DFT Engineer responsible for designing and optimizing DFT architectures for next-generation SpaceX ASICs, coordinating with cross-functional teams across silicon, firmware, validation, and manufacturing. Lead integration of DFT IPs, set up ATPG, and drive post-silicon bringup and ATE debugging to ensure robust testability and yield across Starlink hardware.

Location: Irvine, Austin, Sunnyvale

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Seniority: Sr. Manager level

Key Responsibilities

•Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools.
•Integration and verification of Design for Test (DFT) IPs and fabrics within Subsystems.
•Set up and run Automatic Test Pattern Generation (ATPG) tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows.
•Run and debug non-timing and SDF annotated gate-level simulations.
•Create and validate DFT patterns for post-silicon bringup and also help with ATE debug through all cycles of silicon characterization.

Pay and Benefits

Salary: USD 125,000 - 175,000 annually

Equity and Bonus:Equity

Perks:MedicalVisionDental401kDisabilityParental LeavePaid Leave

Key Requirements

•Bachelor’s degree in electrical engineering, computer engineering, or physics.
•5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing.
•Master’s or PhD in electrical engineering, computer engineering, physics, or related engineering field.
•Extensive experience in post-silicon bringup, including silicon debug, failure analysis, and yield optimization on complex SoCs or ASICs.
•Hands-on experience with Automated Test Equipment (ATE) platforms (e.g., Teradyne, Advantest) for high-volume manufacturing test development and debug.

Experience:5+ yearsSpace

Education:Bachelor's in Electrical Engineering

Skills:Problem-solvingCommunicationCollaboration

Languages:English

Tech Stack:Siemens TessentATPGPerlPythonTclC++

Company Brief

SpaceX

Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.

Industry: Aerospace Manufacturing

Company Size: Enterprise (1,001+ employees)

Growth: Established Company

Valuation: Hectocorn (USD 100B+)

Funding: Series E+

Headquarters: Hawthorne, United States

Founded: 2002

Glassdoor: 4.2

Website LinkedIn

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SpaceX

1 month ago

Sr. ASIC DFT Engineer (Silicon)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Location: Irvine, Austin, Sunnyvale

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Seniority: Sr. Manager level

Key Responsibilities

•Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools.
•Integration and verification of Design for Test (DFT) IPs and fabrics within Subsystems.
•Set up and run Automatic Test Pattern Generation (ATPG) tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows.
•Run and debug non-timing and SDF annotated gate-level simulations.
•Create and validate DFT patterns for post-silicon bringup and also help with ATE debug through all cycles of silicon characterization.

Pay and Benefits

Salary: USD 125,000 - 175,000 annually

Equity and Bonus:Equity

Perks:MedicalVisionDental401kDisabilityParental LeavePaid Leave

Key Requirements

•Bachelor’s degree in electrical engineering, computer engineering, or physics.
•5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing.
•Master’s or PhD in electrical engineering, computer engineering, physics, or related engineering field.
•Extensive experience in post-silicon bringup, including silicon debug, failure analysis, and yield optimization on complex SoCs or ASICs.
•Hands-on experience with Automated Test Equipment (ATE) platforms (e.g., Teradyne, Advantest) for high-volume manufacturing test development and debug.

Experience:5+ yearsSpace

Education:Bachelor's in Electrical Engineering

Skills:Problem-solvingCommunicationCollaboration

Languages:English

Tech Stack:Siemens TessentATPGPerlPythonTclC++

Company Brief

SpaceX

Industry: Aerospace Manufacturing

Company Size: Enterprise (1,001+ employees)

Growth: Established Company

Valuation: Hectocorn (USD 100B+)

Funding: Series E+

Headquarters: Hawthorne, United States

Founded: 2002

Glassdoor: 4.2

Website LinkedIn