DFT Design Engineer

Cadence Design Systems
Austin, San Jose
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 3-12 yearsSkills: ["Collaboration","Problem-solving","Self-driven","Thoroughness","Stakeholder communication"]

Design and implement SoC/ASIC digital Design-for-Test (DFT) flows, including scan chain insertion, compression scan, LBIST, and MBIST. Build and validate ATPG test patterns to meet design test coverage goals, perform failure debug and analysis, and verify/debug Verilog ATPG testbenches. Work across cross-functional teams to improve test coverage and support timing analysis and equivalency checks, optionally using Cadence tools and flows.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Cadence Design Systems
Cadence Design Systems
3 days ago

DFT Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 3 hours agoStatus: Live

Job Summary

Design and implement SoC/ASIC digital Design-for-Test (DFT) flows, including scan chain insertion, compression scan, LBIST, and MBIST. Build and validate ATPG test patterns to meet design test coverage goals, perform failure debug and analysis, and verify/debug Verilog ATPG testbenches. Work across cross-functional teams to improve test coverage and support timing analysis and equivalency checks, optionally using Cadence tools and flows.
Location: Austin, San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Implement DFT tasks for SoC/ASIC digital designs, including scan chain insertion and DFT insertion flows.
  • •Develop and run ATPG pattern generation to achieve design test coverage goals using systematic quality metrics.
  • •Support memory test through MBIST and related scan technologies such as compression scan and LBIST.
  • •Debug and analyze failures to improve fault coverage, including root-cause analysis for simulation mis-compares.
  • •Verify ATPG testbenches and collaborate with cross-functional stakeholders (architecture, design, internal and external customers).

Key Requirements

  • •3–12 years of professional experience in SoC/ASIC digital design with a focus on Design for Test (DFT).
  • •Hands-on knowledge of DFT insertion flows and scan chain insertion (basic insertion using synthesis or other tools).
  • •Experience with compression scan insertion, LBIST, and other scan technologies, including MBIST.
  • •Expertise in Automatic Test Pattern Generation (ATPG) to reach design test coverage goals.
  • •Ability to debug and analyze failures, verify and debug ATPG testbenches, and work with cross-functional stakeholders.
Experience:3-12 yearsSoC/ASICDFTATPG
Skills:CollaborationProblem-solvingSelf-drivenThoroughnessStakeholder communication
Tech Stack:DFT insertion flowsScan chain insertionCompression scanLBISTMBISTATPGVerilogJTAG 1149.1/6IEEE1500IEEE1687Timing analysisEquivalency checksSynthesisDebugging

Eligibility

Nationality:US National

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
Glassdoor
Glassdoor: 3.9
WebsiteLinkedInGlassdoor