Cadence Design Systems

3 months ago

Senior Principal Functional Verification Engineer - Applied ML

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 7 hours agoStatus: Live

Job Summary

Lead pre-silicon verification efforts by applying ML techniques to formal verification, SV/UVM and related methodologies. Collaborate with ML and software teams to design AI-enabled verification strategies for Cadence's ChipStack AI ecosystem, leveraging LLMs and AI-powered EDA tools to accelerate chip design and verification. Interact with customers to capture requirements and drive innovative verification solutions for next-generation semiconductor designs in a fast-paced, interdisciplinary environment.

Location: Israel

Workplace: Onsite

Employment Type: Full time

Job Function: Solutions Engineering & Sales Engineering

Key Responsibilities

•Contribute to the application of machine learning techniques aimed at streamlining traditional pre-silicon functional verification methodologies like formal verification and UVM.
•Develop agentic AI solutions using LLMs and latest ML technologies to accelerate pre-silicon Design Verification process.
•Employ AI enhanced Electronic Design Automation (EDA) tools to improve and expedite both the design and verification lifecycles.
•Engage directly with customers to understand requirements and deliver innovative, practical verification strategies.
•Collaborate effectively with machine learning and software engineering teams to validate output correctness, efficiency, and quality.

Key Requirements

•BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
•Proven expertise of more than 3 years in at least one of the pre-silicon ASIC verification methodologies such as Formal, SV/UVM and/or OVM
•Advanced skills in debugging pre-silicon verification failures using waveform viewers and simulation analysis tools
•Hands-on experience with industry standard EDA tools (e.g., Jasper, Xcelium, IMC)
•Strong programming skills in Verilog, System Verilog and Python

Experience:SemiconductorEDAAI

Education:Bachelor's

Skills:CommunicationTeamworkProblem-solvingSelf-motivatedContinuous learning

Tech Stack:VerilogSystemVerilogPythonJasperXceliumIMCUVMOVMFormal verificationWaveform viewers

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

3 months ago

Senior Principal Functional Verification Engineer - Applied ML

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 7 hours agoStatus: Live

Job Summary

Location: Israel

Workplace: Onsite

Employment Type: Full time

Job Function: Solutions Engineering & Sales Engineering

Key Responsibilities

•Contribute to the application of machine learning techniques aimed at streamlining traditional pre-silicon functional verification methodologies like formal verification and UVM.
•Develop agentic AI solutions using LLMs and latest ML technologies to accelerate pre-silicon Design Verification process.
•Employ AI enhanced Electronic Design Automation (EDA) tools to improve and expedite both the design and verification lifecycles.
•Engage directly with customers to understand requirements and deliver innovative, practical verification strategies.
•Collaborate effectively with machine learning and software engineering teams to validate output correctness, efficiency, and quality.

Key Requirements

•BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
•Proven expertise of more than 3 years in at least one of the pre-silicon ASIC verification methodologies such as Formal, SV/UVM and/or OVM
•Advanced skills in debugging pre-silicon verification failures using waveform viewers and simulation analysis tools
•Hands-on experience with industry standard EDA tools (e.g., Jasper, Xcelium, IMC)
•Strong programming skills in Verilog, System Verilog and Python

Experience:SemiconductorEDAAI

Education:Bachelor's

Skills:CommunicationTeamworkProblem-solvingSelf-motivatedContinuous learning

Tech Stack:VerilogSystemVerilogPythonJasperXceliumIMCUVMOVMFormal verificationWaveform viewers

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor