Substrate IC Package Layout Design Engineer

Etched
San Jose
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 10+ yearsEducation: bachelorsSkills: ["Analytical skills","Cross-functional collaboration","Technical guidance"]

Design end-to-end complex IC substrate packages for high-power AI processors and accelerators, including large multi-layer (>50mm) layouts and dense routing. Optimize power delivery and high-speed signal routing up to and beyond 50GHz in partnership with SI/PI and system teams. Drive CoWoS (chip-on-wafer-on-substrate) interposer optimization, perform DRC/LVS verification, and ensure design feasibility with packaging and OSAT partners.

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FursaFursa
Etched
Etched
4 days ago

Substrate IC Package Layout Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 8 hours agoStatus: Live
Reposted: similar role first listed 1 year ago

Job Summary

Design end-to-end complex IC substrate packages for high-power AI processors and accelerators, including large multi-layer (>50mm) layouts and dense routing. Optimize power delivery and high-speed signal routing up to and beyond 50GHz in partnership with SI/PI and system teams. Drive CoWoS (chip-on-wafer-on-substrate) interposer optimization, perform DRC/LVS verification, and ensure design feasibility with packaging and OSAT partners.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Lead end-to-end design and development of complex IC substrate layouts for high-power AI processors and accelerators.
  • •Design large (>50mm) multi-layer substrate packages with high pin counts and dense routing requirements.
  • •Ensure robust power delivery for high-power (700W+) custom silicon solutions.
  • •Develop and validate high-speed (>50GHz) signal routing solutions in collaboration with SI/PI engineers.
  • •Optimize CoWoS (chip-on-wafer-on-substrate) interposer designs and perform DRC/LVS verification with ongoing documentation and design review support.

Pay and Benefits

Perks:Health InsuranceDentalVisionHousing SubsidyRelocation SupportWellness Stipend

Key Requirements

  • •Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • •10+ years of experience in IC substrate layout design for high-performance processors or accelerators.
  • •Extensive experience with large substrate packages (>50mm) and complex high-density layouts.
  • •Proven experience designing high-power (700W+) packages with robust power delivery networks.
  • •Expertise in high-speed signaling design (>50GHz) with mitigation of signal integrity issues like crosstalk and reflections.
Experience:10+ yearsAISemiconductorsHigh-performance computingHardware designAdvanced packaging
Education:Bachelor's in Electrical Engineering or Computer Engineering (or related field)
Skills:Analytical skillsCross-functional collaborationTechnical guidance
Tech Stack:IC substrate layoutCoWoSChip-on-Wafer-on-SubstrateDRCLVSAllegro Package Designer

Company Brief

Etched
Designs transformer‑specialized AI inference ASICs (product: Sohu) to accelerate large‑language‑model workloads, working with TSMC for fabrication and targeting energy‑efficient inference performance.
Industry: Hardware Devices
Company Size: Medium (51 to 250 employees)
Growth: Early Stage Startup
Valuation: Unicorn (USD 1B+)
Funding: Series A
Headquarters: San Jose, United States
Founded: 2022
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