Principal Engineer, High‑Speed RTL Design

Micron Technology
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Skills: ["Independent problem-solving","Ownership","Risk management","Effective collaboration"]

Design and implement timing-critical high-speed RTL blocks for complex system-on-chip subsystems, including FSM control, power-up/shutdown and mode transitions, register/configuration logic, and telemetry datapaths. Write nanometer process-aware RTL robust to setup/hold, clock skew/uncertainty, false/multi-cycle paths, and PVT variation. Own CDC, reset/power-aware logic, integrate/debug RTL, and partner with verification engineers to drive timing closure and design review documentation.

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FursaFursa
Micron Technology
Micron Technology
1 day ago

Principal Engineer, High‑Speed RTL Design

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Last checked: 9 hours agoStatus: Live

Job Summary

Design and implement timing-critical high-speed RTL blocks for complex system-on-chip subsystems, including FSM control, power-up/shutdown and mode transitions, register/configuration logic, and telemetry datapaths. Write nanometer process-aware RTL robust to setup/hold, clock skew/uncertainty, false/multi-cycle paths, and PVT variation. Own CDC, reset/power-aware logic, integrate/debug RTL, and partner with verification engineers to drive timing closure and design review documentation.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Design and implement timing-critical RTL blocks including FSMs, power-up/shutdown, and mode-transition logic.
  • •Develop nanometer process-aware RTL that is robust to setup/hold, clock skew/uncertainty, multi-cycle/false-path constraints, and PVT variation.
  • •Implement and review clock-domain crossing (CDC), and design reset and initialization logic for predictable startup and recovery.
  • •Integrate RTL blocks into larger subsystems/top-level designs and resolve port, clock/reset, and mode interaction issues; debug using simulation and tool feedback.
  • •Partner with verification engineers and support timing closure by clarifying intent/corners and refining logic for synthesis and place-and-route issues.

Pay and Benefits

Perks:Paid LeaveLearning BudgetWellness StipendHealth InsuranceDentalVisionEquity

Key Requirements

  • •Strong proficiency in SystemVerilog/Verilog RTL and timing-critical control logic.
  • •Experience designing and implementing FSMs and reset synchronization.
  • •Hands-on knowledge of clock-domain crossing (CDC) concepts and synchronization techniques.
  • •Ensure RTL robustness for tight setup/hold margins, clock skew/uncertainty, multi-cycle/false-path constraints, and PVT variation.
  • •Familiarity with RTL lint and CDC checks, synthesis and STA reports, DFT-friendly RTL practices, UPF and LEC; plus debugging RTL issues in late integration stages.
Skills:Independent problem-solvingOwnershipRisk managementEffective collaboration
Tech Stack:SystemVerilogVerilogRTLFSMCDCSimulation waveformsStatic timing analysis (STA)RTL lintUPFLECPythonTclDFTECOPlace-and-route

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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