Engineer, APTD CEM – Advanced Packaging Wafer Level Technology Engineering
Singapore
Workplace: OnsiteFull timeFunction: Industrial, Process & Manufacturing EngineeringEducation: bachelorsSkills: ["Analytical thinking","Critical thinking","Communication","Collaboration","Continuous learning"]Develop and improve wafer-level semiconductor process conditions for advanced packaging, including wafer thinning and backside metal interconnect. Upgrade process capabilities to reduce production costs and support technology scaling for next nodes. Evaluate equipment and materials, perform process and quality improvement using measurement/inspection/testing data, and drive correlations to identify improvements. Collaborate across package integration, assembly engineering, wafer fab, product engineering, and global quality to ensure smooth transfers from development through high-volume manufacturing.
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