Sr Digital Design Engineer

Micron Technology
Boise
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 4+ yearsEducation: mastersSkills: ["Communication","Problem-solving","Teamwork","Collaboration"]

Design and deliver RTL for advanced DRAM digital and mixed-signal blocks, taking features from specification through RTL-to-GDS flow. Own front-end quality checks such as linting, CDC/RDC analysis, synthesis, timing constraint (SDC) development, and timing closure across operating scenarios. Partner with architecture, verification, and physical design teams to optimize power, performance, area (PPA), and improve design methodologies and automation for faster, higher-quality delivery.

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FursaFursa
Micron Technology
Micron Technology
3 weeks ago

Sr Digital Design Engineer

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Last checked: 18 hours agoStatus: Live

Job Summary

Design and deliver RTL for advanced DRAM digital and mixed-signal blocks, taking features from specification through RTL-to-GDS flow. Own front-end quality checks such as linting, CDC/RDC analysis, synthesis, timing constraint (SDC) development, and timing closure across operating scenarios. Partner with architecture, verification, and physical design teams to optimize power, performance, area (PPA), and improve design methodologies and automation for faster, higher-quality delivery.
Location: Boise
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Design, develop, and deliver RTL for complex DRAM digital and mixed-signal blocks aligned to product specifications and performance targets.
  • •Run front-end design quality checks (linting, CDC/RDC analysis), perform logic synthesis, develop timing constraints, and drive timing closure.
  • •Collaborate across architecture, verification, and physical design teams to optimize power, performance, area (PPA), and overall design quality.
  • •Develop and maintain synthesis and timing constraints (SDC), analyze timing reports, and address timing closure across multiple operating scenarios.
  • •Improve design methodologies, automation, and RTL-to-GDS flow efficiency to enhance design quality and time-to-market.

Pay and Benefits

Perks:Health InsurancePaid Leave

Key Requirements

  • •Master’s degree in Electrical Engineering (or equivalent) with 4+ years of experience, or Bachelor’s degree with 5+ years of experience in digital ASIC/RTL design.
  • •Develop RTL for complex digital designs from specification through implementation handoff.
  • •Strong ASIC front-end design flow knowledge: RTL design, functional verification, logic synthesis, CDC/RDC analysis, and static timing analysis (STA).
  • •Experience developing and maintaining design constraints (SDC), including clocks, timing exceptions, I/O constraints, and multi-mode multi-corner timing.
  • •Proficiency with Verilog/SystemVerilog and industry-standard simulation tools, including low-power methodologies with UPF-based power intent and PPA optimization.
Experience:4+ yearsSemiconductorsDRAMMemoryMixed-signalDigital ASICRTLLow-power design
Education:Master's in Electrical Engineering
Skills:CommunicationProblem-solvingTeamworkCollaboration
Tech Stack:RTLRTL-to-GDSDRAMVerilogSystemVerilogLogic synthesisStatic timing analysis (STA)CDC/RDC analysisSDCUPFLow-power designTiming constraintsTiming closureLintingSimulation toolsPPA optimization

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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