Principal ASIC Design Engineer (Silicon Engineering)

SpaceX
Palo Alto
Workplace: OnsiteFull timeUSD 220,000 - 355,000Function: Design (Product/UX/UI/Visual)Experience: 10+ yearsEducation: bachelorsSkills: ["Problem-solving","Collaboration","Teamwork","Individual contribution","Learning mindset"]

Develop next-generation ASICs for space and ground Starlink infrastructure. Own RTL micro-architecture and implementation in Verilog/SystemVerilog, integrate and deliver fully verified, synthesis/timing-clean designs, and partner with verification for complete coverage. Provide timing constraints and support physical implementation (synthesis, timing closure, formal checks), and contribute to silicon bring-up and validation. Work with cross-disciplinary teams spanning systems, firmware, architecture, design, and validation.

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FursaFursa
SpaceX
SpaceX
23 hours ago

Principal ASIC Design Engineer (Silicon Engineering)

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Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live

Job Summary

Develop next-generation ASICs for space and ground Starlink infrastructure. Own RTL micro-architecture and implementation in Verilog/SystemVerilog, integrate and deliver fully verified, synthesis/timing-clean designs, and partner with verification for complete coverage. Provide timing constraints and support physical implementation (synthesis, timing closure, formal checks), and contribute to silicon bring-up and validation. Work with cross-disciplinary teams spanning systems, firmware, architecture, design, and validation.
Location: Palo Alto
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Evaluate architectural trade-offs based on features, performance requirements, and system limitations.
  • •Define micro-architecture and implement RTL in Verilog/SystemVerilog; integrate in top level and deliver fully verified, synthesis/timing-clean designs.
  • •Collaborate with the verification team to ensure design aspects are covered and verified.
  • •Provide timing constraints for IPs and support physical implementation (synthesis, timing closure, formality checks).
  • •Participate in silicon bring-up and validation.

Pay and Benefits

Salary: USD 220,000 - 355,000
Perks:Health InsuranceVisionDental401kPaid ParentalPaid Leave

Key Requirements

  • •Bachelor’s degree in electrical engineering, computer engineering, or computer science.
  • •10+ years of experience in RTL implementation.
  • •Ability to solve complex problems including clock domain crossings and power optimization.
  • •ASIC/SoC system integration experience.
  • •Experience with standard bus protocols (e.g., AXI, AHB) and high-speed, low-power design techniques.
Experience:10+ yearsASICSoCSpaceSatellite
Education:Bachelor's
Skills:Problem-solvingCollaborationTeamworkIndividual contributionLearning mindset
Languages:English
Tech Stack:VerilogSystemVerilogRTLRTL implementationRTL micro-architectureRTL integrationPythonEDA toolsHDL simulatorsHDL lint toolsAXIAHBSynthesisTiming closureFormalityClock domain crossingsPower optimizationEmbedded CPU subsystems

Eligibility

Nationality:US National

Company Brief

SpaceX
Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.
Industry: Aerospace Manufacturing
Company Size: Enterprise (1,001+ employees)
Growth: Established Company
Valuation: Hectocorn (USD 100B+)
Funding: Series E+
Headquarters: Hawthorne, United States
Founded: 2002
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Glassdoor: 4.2
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