Memory Electrical Validation Engineer

Intel
United States
Workplace: OnsiteFull timeUSD 122,440 - 232,190 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 1+ yearsSkills: ["Technical collaboration","Debugging","Problem-solving"]

Join Intel’s Memory Validation Team to validate the electrical performance of memory IO interfaces for mobile and desktop CPU products. Define electrical validation strategies, execute signal integrity and margin validation, and develop Memory Reference Code (MRC) requirements to improve quality and stability. Debug electrical design features, drive Design of Experiments (DOEs) to root cause with circuit and logic teams, and collaborate across architecture and pre-silicon verification to ensure robust IO architecture validation.

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FursaFursa
Intel
Intel
4 months ago

Memory Electrical Validation Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 12 minutes agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Join Intel’s Memory Validation Team to validate the electrical performance of memory IO interfaces for mobile and desktop CPU products. Define electrical validation strategies, execute signal integrity and margin validation, and develop Memory Reference Code (MRC) requirements to improve quality and stability. Debug electrical design features, drive Design of Experiments (DOEs) to root cause with circuit and logic teams, and collaborate across architecture and pre-silicon verification to ensure robust IO architecture validation.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

  • •Define electrical validation strategies for memory IO interfaces to meet production goals and optimized performance targets.
  • •Validate circuit analog performance, electrical signal integrity compliance, and system-level margin for stable operation.
  • •Develop and optimize Memory Reference Code (MRC) requirements, analyzing MRC steps/values for margin and quality improvements.
  • •Design and execute validation procedures, infrastructure, and systems margin analysis; debug electrical design features to resolve functional and triage failures.
  • •Drive DOEs to root cause with circuit and logic design teams, and collaborate with architecture, design, and pre-silicon verification to ensure robust IO architecture validation.

Pay and Benefits

Salary: USD 122,440 - 232,190 annually
Perks:Health InsuranceRetirementPaid Leave

Key Requirements

  • •Bachelor’s with 4+ years, Master’s with 3+ years, or PhD with 1+ years in Electrical Engineering (or related).
  • •3+ years in memory electrical validation, including signal integrity and signal margin validation (SIV/SMV).
  • •3+ years in memory physical design or mixed-signal IP electrical validation.
  • •3+ years in analog and mixed-signal fundamentals, electrical calibration methodology, and memory validation/debug processes.
  • •Preferred: 5+ years in high-speed mixed-signal design or signal integrity analysis, plus familiarity with DDR5/LP5 and MRC FW components for debug root cause.
Experience:1+ years
Education:
Skills:Technical collaborationDebuggingProblem-solving
Tech Stack:MRCDDR5LP5SIV/SMVDOEs

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
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