Sr. RFIC Layout Designer (Starshield Silicon)

Lead RFIC and mixed-signal layout for Starshield silicon, working with IC designers and chip leads to define chip floorplans, power/ground strategies, and pad locations. Execute custom RF/analog block layout with careful matching and parasitic minimization, run design/electrical rule checks, and integrate top-level layouts including ESD structures and tape-out deliverables. Collaborate across teams and trial new EDA tooling to improve layout techniques for space and ground infrastructure.