Physical Design Engineer (Bengaluru)

Cerebras
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Skills: ["Learnability","Continuous learning","Curiosity","Coachability","Cross-team collaboration"]

Work on wafer-scale physical design for an AI chip by performing synthesis, place and route, timing closure, and block sign-off. Own physical verification and implementation details, including block/subsystem timing closure and full-chip floorplanning and integration. Partner closely with the RTL team and full-chip integration flow, using tools such as ICV/Calibre to resolve DRC/LVS and performing IR/EM analysis. Enable flow enhancements using Tcl and Python.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Cerebras
Cerebras
4 months ago

Physical Design Engineer (Bengaluru)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 16 hours agoStatus: Live

Job Summary

Work on wafer-scale physical design for an AI chip by performing synthesis, place and route, timing closure, and block sign-off. Own physical verification and implementation details, including block/subsystem timing closure and full-chip floorplanning and integration. Partner closely with the RTL team and full-chip integration flow, using tools such as ICV/Calibre to resolve DRC/LVS and performing IR/EM analysis. Enable flow enhancements using Tcl and Python.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Perform physical design tasks including synthesis, place and route, timing, and block closure/sign-off.
  • •Participate in all aspects of physical design implementation and work closely with the RTL team.
  • •Support full-chip integration of blocks and contribute to block/subsystem and full-chip physical verification.
  • •Resolve DRC and LVS issues at block and full-chip levels using ICV or Calibre.
  • •Optimize for power/performance and area and perform IR/EM analysis and resolution; develop flow enhancements with Tcl/Python.

Key Requirements

  • •7+ years of physical design/verification experience.
  • •Strong experience in block/subsystem timing closure and block level/full-chip physical verification methodology.
  • •Expertise in optimizing power/performance and area, including block physical design concepts such as PDV and IR.
  • •Expertise using ICV or Calibre tools to resolve block and full-chip DRC and LVS issues, plus IR/EM analysis and resolution.
  • •Good understanding of full-chip floor-planning and integration; strong scripting ability in Tcl and Python (flow enhancements).
Experience:HardwarePhysical designVerificationAI chips
Education:
Skills:LearnabilityContinuous learningCuriosityCoachabilityCross-team collaboration
Tech Stack:TclPythonICVCalibreSynopsysDRCLVSIR/EMPDVSTASynthesisPlace and routeFloor-planning

Company Brief

Cerebras
Designs and builds wafer-scale AI accelerators and systems for large-scale deep learning workloads, delivering specialized hardware and software to accelerate model training and inference for enterprises and research institutions.
Industry: Hardware Devices
Company Size: Large (251 to 1,000 employees)
Growth: Scaleup
Headquarters: Sunnyvale, United States
Founded: 2016
WebsiteLinkedIn