Cadence Design Systems

4 weeks ago

Design Architect

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 23 hours agoStatus: Live

Job Summary

Join Cadence as a Design Architect contributing to digital architecture, RTL design, and low-power implementations for SerDes IP. You’ll drive architecture from concept to RTL, coordinate with verification and analog teams across geographies, and apply AI-assisted design practices and multi-language toolflows to ensure IP quality within tight project timelines.

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Solutions Engineering & Sales Engineering

Key Responsibilities

•Define and drive the digital architecture from micro-architecture to RTL implementation, refining features and requirements throughout the design process.
•Collaborate with design architects, digital verification, project management, and analog teams across geographies to ensure IP quality and timely delivery.
•Oversee synthesis, constraint generation, power management and DFT, and contribute to power-aware design strategies (low-power features such as power islands and state retention).
•Work with verification teams to specify coverage points, develop testing strategies, and create stimulus for corner conditions and SVAs.
•Leverage familiarity with uC-based subsystems and AI-assisted design practices to optimize SerDes IP and related blocks.

Key Requirements

•18-20 years of experience in Digital Design and Architecture.
•Proven experience in Design Architecture, Design implementation, Embedded uC Designs, Synthesis and SDC Creation, Scripting of design automation, Debugging verification test cases / SVA’s to cover the design.
•Knowledge of existing Serial standards such as PCIe, USB, Ethernet.
•Comfortable interacting with SSG development, Mixed-signal, Verification and Analog teams.
•Knowledge of System Verilog, Python, C/C++, etc, are a plus; Revision control tools such as Perforce, Git, SVN are a plus; Bachelor’s degree minimum, Master’s preferred.

Experience:18-20 yearsSemiconductorsEmbedded systemsDigital design

Education:Bachelor's

Skills:SystemVerilogPythonCC++SVAScriptingDesign automationSynthesisDFTVerificationPerforceGitSvn

Languages:English

Tech Stack:SystemVerilogPythonC++CPerforceGitSVNRTLSynthesisDFTSVA

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

4 weeks ago

Design Architect

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 23 hours agoStatus: Live

Job Summary

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Solutions Engineering & Sales Engineering

Key Responsibilities

•Define and drive the digital architecture from micro-architecture to RTL implementation, refining features and requirements throughout the design process.
•Collaborate with design architects, digital verification, project management, and analog teams across geographies to ensure IP quality and timely delivery.
•Oversee synthesis, constraint generation, power management and DFT, and contribute to power-aware design strategies (low-power features such as power islands and state retention).
•Work with verification teams to specify coverage points, develop testing strategies, and create stimulus for corner conditions and SVAs.
•Leverage familiarity with uC-based subsystems and AI-assisted design practices to optimize SerDes IP and related blocks.

Key Requirements

•18-20 years of experience in Digital Design and Architecture.
•Proven experience in Design Architecture, Design implementation, Embedded uC Designs, Synthesis and SDC Creation, Scripting of design automation, Debugging verification test cases / SVA’s to cover the design.
•Knowledge of existing Serial standards such as PCIe, USB, Ethernet.
•Comfortable interacting with SSG development, Mixed-signal, Verification and Analog teams.
•Knowledge of System Verilog, Python, C/C++, etc, are a plus; Revision control tools such as Perforce, Git, SVN are a plus; Bachelor’s degree minimum, Master’s preferred.

Experience:18-20 yearsSemiconductorsEmbedded systemsDigital design

Education:Bachelor's

Skills:SystemVerilogPythonCC++SVAScriptingDesign automationSynthesisDFTVerificationPerforceGitSvn

Languages:English

Tech Stack:SystemVerilogPythonC++CPerforceGitSVNRTLSynthesisDFTSVA

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor