4 months ago

Lead Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 2 hours agoStatus: Live

Job Summary

Lead Verification Engineer specializing in pre-silicon verification with ML-enabled AI techniques. You will collaborate with ML engineers and software teams to develop AI-driven verification strategies, apply ML to formal and UVM verification, and leverage AI-powered EDA tools to accelerate design and verification lifecycles, ensuring high-quality verification outcomes for next-generation semiconductor designs.

Location: Noida, Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Administration & Executive Assistance

Key Responsibilities

•Contribute to applying machine learning techniques to streamline pre-silicon functional verification methodologies (e.g., formal verification, UVM).
•Develop agentic AI solutions using LLMs and ML technologies to accelerate pre-silicon Design Verification processes.
•Employ AI-enhanced EDA tools to improve and expedite both design and verification lifecycles.
•Engage directly with customers to understand requirements and deliver innovative verification strategies.
•Collaborate with ML and software engineering teams to validate output correctness, efficiency, and quality.

Key Requirements

•Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field.
•3-6+ years of experience in pre-silicon ASIC verification methodologies such as Formal, SV/UVM and/or OVM.
•Advanced skills in debugging pre-silicon verification failures using waveform viewers and simulation analysis tools.
•Hands-on experience with industry standard EDA tools (e.g., Jasper, Xcelium, IMC).
•Strong programming skills in Verilog, SystemVerilog and Python

Experience:3-6 yearsSemiconductorASICEDAMachine learning

Education:Bachelor's

Skills:CommunicationTeamworkProblem-solvingSelf-motivatedContinuous learning

Languages:English

Tech Stack:VerilogSystemVerilogPythonLLMsJasperXceliumIMCUVMFormalSV/UVM

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

4 months ago

Lead Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 2 hours agoStatus: Live

Job Summary

Location: Noida, Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Administration & Executive Assistance

Key Responsibilities

•Contribute to applying machine learning techniques to streamline pre-silicon functional verification methodologies (e.g., formal verification, UVM).
•Develop agentic AI solutions using LLMs and ML technologies to accelerate pre-silicon Design Verification processes.
•Employ AI-enhanced EDA tools to improve and expedite both design and verification lifecycles.
•Engage directly with customers to understand requirements and deliver innovative verification strategies.
•Collaborate with ML and software engineering teams to validate output correctness, efficiency, and quality.

Key Requirements

•Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field.
•3-6+ years of experience in pre-silicon ASIC verification methodologies such as Formal, SV/UVM and/or OVM.
•Advanced skills in debugging pre-silicon verification failures using waveform viewers and simulation analysis tools.
•Hands-on experience with industry standard EDA tools (e.g., Jasper, Xcelium, IMC).
•Strong programming skills in Verilog, SystemVerilog and Python

Experience:3-6 yearsSemiconductorASICEDAMachine learning

Education:Bachelor's

Skills:CommunicationTeamworkProblem-solvingSelf-motivatedContinuous learning

Languages:English

Tech Stack:VerilogSystemVerilogPythonLLMsJasperXceliumIMCUVMFormalSV/UVM

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor