Senior Principal Software Engineer - Accelerated Verification IP

Cadence Design Systems
San Jose
Workplace: OnsiteFull timeFunction: Software EngineeringEducation: bachelorsSkills: ["Verilog","RTL","PCIe","CXL","UVM","Emulation","Virtual platforms","Debugging"]

Lead design and verification of PCIe/CXL features for high-performance IO and memory coherence, building next-generation AVIP and Virtual Bridge components. Architect and implement RTL in Verilog, drive bring-up for CXL.io/cache/mem, and coordinate cross-team interoperability across hardware, emulation, and virtual platforms to ensure PCIe Gen7/CXL 2.x/3.x readiness.

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Cadence Design Systems
Cadence Design Systems
4 months ago

Senior Principal Software Engineer - Accelerated Verification IP

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Source: Company careers pageValidated by: Fursa AI
Last checked: 3 hours agoStatus: Live

Job Summary

Lead design and verification of PCIe/CXL features for high-performance IO and memory coherence, building next-generation AVIP and Virtual Bridge components. Architect and implement RTL in Verilog, drive bring-up for CXL.io/cache/mem, and coordinate cross-team interoperability across hardware, emulation, and virtual platforms to ensure PCIe Gen7/CXL 2.x/3.x readiness.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Software Engineering

Key Responsibilities

  • •Design and enhance PCIe/CXL AVIP components (agents, monitors, scoreboards, sequencers, coverage, error injection).
  • •Develop Virtual Bridge components connecting virtual platforms/emulators/FW to RTL (traffic modeling, performance, debug).
  • •Own feature bring-up for CXL.io/CXL.cache/CXL.mem, IDE/security, RAS, switching/fabric (CXL 3.x).
  • •Deliver compliance and interoperability scenarios; drive customer escalations and cross-team integration.

Key Requirements

  • •BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
  • •Experience with PCIe and/or CXL design/verification, deep protocol-layer knowledge (LTSSM, DLL/TLP, flow control, ordering)
  • •Proficiency in Verilog RTL design and debug
  • •Experience with emulation/acceleration or hybrid (virtual + RTL) flows; solid debug skills (waveforms, checkers, coverage)
  • •Nice to have PCIe Gen6/CXL 3.x fabric features (multi-level switching, global fabric attach, pooling)
Experience:SemiconductorHardwareIP verificationEDA
Education:Bachelor's
Skills:VerilogRTLPCIeCXLUVMEmulationVirtual platformsDebugging
Languages:English
Tech Stack:VerilogPCIeCXLUVMRTLEmulationVirtual platforms

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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