STA Silicon Design Engineer

AMD
Bengaluru
Full timeINR 3,338,160 - 4,768,800 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: bachelorsSkills: []

Develop and validate complex multi-mode/multi-corner timing constraints compatible with RTL and signoff. Ensure SDC constraint quality, run pre-route timing checks, and drive QoR cleanups to resolve SDC issues. Own timing closure for sub-chips through full-chip, including interface timing and DRV closure, and generate/lead timing ECOs using DMSA/Tweaker. Use industry STA methodology and Tcl scripting in EDA and Linux environments.

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FursaFursa
AMD
AMD
1 day ago

STA Silicon Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 7 hours agoStatus: Live

Job Summary

Develop and validate complex multi-mode/multi-corner timing constraints compatible with RTL and signoff. Ensure SDC constraint quality, run pre-route timing checks, and drive QoR cleanups to resolve SDC issues. Own timing closure for sub-chips through full-chip, including interface timing and DRV closure, and generate/lead timing ECOs using DMSA/Tweaker. Use industry STA methodology and Tcl scripting in EDA and Linux environments.
Location: Bengaluru
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Develop multi-mode/multi-corner timing constraints compatible with RTL and signoff.
  • •Validate and improve constraints quality (SDC) using industry tools like Fishtail and GCA.
  • •Conduct pre-route timing checks and QoR cleanups to eliminate SDC issues and ensure quality STA handoff.
  • •Drive timing closure for sub-chips/subsystems or full chip, including interface timing closure and DRV closure.
  • •Generate timing ECOs using tools like DMSA/Tweaker and lead subsystem/subchip/FC timing closure activities.

Pay and Benefits

Salary: INR 3,338,160 - 4,768,800 annually

Key Requirements

  • •8+ years of experience building timing constraints for IPs/blocks and full-chip implementation in flat or hierarchical flows.
  • •Strong SDC knowledge, including OCV/AOCV/POCV analysis and corner definitions for timing signoff.
  • •EDA timing tool competence, including Synopsys Design Compiler/Primetime and/or Spyglass/Fishtail/Tweaker.
  • •Strong Tcl/scripting capability in both EDA environments and standalone Linux Tcl shells.
  • •Experience with timing closure of high-frequency blocks/subsystems, DFT modes requirements, and ECO implementation.
Experience:8+ years
Education:Bachelor's in Computer Engineering / Electrical Engineering
Tech Stack:STATiming constraintsSDCRTLSignoffFishtailGCATclLinuxSynopsys Design CompilerPrimetimeSpyglassDMSATweakerDFTOCVAOCVPOCVECOQoR

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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