Senior ASIC Design Engineer - DFX

Design-for-Test (DFX) engineering for next-generation SoC products, shaping the architecture, implementation, and verification of DFT IPs across the silicon lifecycle. Own DFT IP such as fuse controller design, develop and scale DFT methodologies, align feature sets with architects and cross-functional teams, and build full-chip functional and DFT test plans. Support post-silicon bring-up with debug and issue resolution, while mentoring junior engineers.