Senior ASIC Design Engineer - DFX

NVIDIA
Santa Clara
Workplace: OnsiteFull timeUSD 168,000 - 310,500 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Communication","Collaborative mindset","Mentoring","Problem-solving"]

Design-for-Test (DFX) engineering for next-generation SoC products, shaping the architecture, implementation, and verification of DFT IPs across the silicon lifecycle. Own DFT IP such as fuse controller design, develop and scale DFT methodologies, align feature sets with architects and cross-functional teams, and build full-chip functional and DFT test plans. Support post-silicon bring-up with debug and issue resolution, while mentoring junior engineers.

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FursaFursa
NVIDIA
NVIDIA
1 month ago

Senior ASIC Design Engineer - DFX

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 22 hours agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Design-for-Test (DFX) engineering for next-generation SoC products, shaping the architecture, implementation, and verification of DFT IPs across the silicon lifecycle. Own DFT IP such as fuse controller design, develop and scale DFT methodologies, align feature sets with architects and cross-functional teams, and build full-chip functional and DFT test plans. Support post-silicon bring-up with debug and issue resolution, while mentoring junior engineers.
Location: Santa Clara
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Own the architecture and design of fuse controller and other DFT IPs for cutting-edge SoC designs.
  • •Develop, deploy, and enhance DFT methodologies for scalability and future product needs.
  • •Define and align feature sets with architects, platform, and software teams.
  • •Partner with design, verification, synthesis, timing, and backend teams to ensure cohesive integration.
  • •Create and execute functional and DFT full-chip verification test plans, supporting post-silicon bring-up with debug and issue resolution.

Pay and Benefits

Salary: USD 168,000 - 310,500 annually
Perks:Equity

Key Requirements

  • •Bachelors degree (or equivalent) with 8+ years experience, or Master’s degree in Electrical Engineering (or related) with 6+ years experience.
  • •5+ years hands-on experience in SoC architecture, RTL design, and verification.
  • •Strong RTL development and micro-architecture proficiency using Verilog (UVM experience is a plus).
  • •Deep expertise in DFT design, methodology, and implementation.
  • •Experience with post-silicon bring-up on ATE, including pattern formats, test program development, and failure analysis.
Experience:SemiconductorsSoCPost-siliconDFT
Education:Bachelor's
Skills:CommunicationCollaborative mindsetMentoringProblem-solving
Tech Stack:VerilogUVMPythonPerlTclRTLSoCDFTATESTAPlace & routePower optimization

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
Glassdoor
Glassdoor: 4.3
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