Principal Engineer , ASIC Analog Design

Micron Technology
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: mastersSkills: ["Mentoring"]

Work on high-speed PHY builds for the newest technology nodes (12nm and below), taking ownership of analog sub-blocks inside the PHY. You will drive specification and implementation across transistor/block-level design, mixed-mode simulation, reliability, and simulation correlations during silicon bring-up. Partner with mask/layout teams, create IP EDA views (including Verilog-A and timing/abstracts), and participate in internal/customer design reviews while mentoring entry-level engineers.

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Micron Technology
Micron Technology
5 days ago

Principal Engineer , ASIC Analog Design

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Job Summary

Work on high-speed PHY builds for the newest technology nodes (12nm and below), taking ownership of analog sub-blocks inside the PHY. You will drive specification and implementation across transistor/block-level design, mixed-mode simulation, reliability, and simulation correlations during silicon bring-up. Partner with mask/layout teams, create IP EDA views (including Verilog-A and timing/abstracts), and participate in internal/customer design reviews while mentoring entry-level engineers.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Own analog sub-block specification and implementation inside the PHY, covering transistor and block-level design, simulation, reliability, and mixed-mode simulations.
  • •Drive layout of sophisticated blocks through mask designers while conforming to process rules and DFM requirements.
  • •Create IP EDA views (e.g., Behavioral/Verilog-A, timing views, and abstract views) to support verification and simulation.
  • •Participate in silicon bring-up and characterization, performing correlations against models and simulations.
  • •Mentor and supervise entry-level engineers and participate in design reviews (internally and potentially with customers) to explain design choices and robustness.

Pay and Benefits

Perks:Paid LeaveLearning BudgetWellness StipendHealth InsuranceEquity

Key Requirements

  • •Circuit design experience in analog/mixed-signal CMOS for deep sub-micron technologies (2–28nm) for high-speed memory interfaces or SerDes.
  • •Experience taking full ownership of analog sub-blocks such as PLL, DLL, CDR, high-speed receivers with equalization, and transmitter front ends/data paths.
  • •Experience with TX/RX equalization (FFE/CTLE/DFE) and various CDR and clocking architectures.
  • •Experience with FinFET (10nm and below) and block-level specification using a link budget.
  • •Hands-on use of tools such as Cadence ADE and Spectre, plus Verilog-A/AMS verification and EM/IR flows; also knowledge of ESD and lab testing/validation data.
Experience:5+ yearsHigh-speed memory interfacesSerDes
Education:Master's in Electronics
Skills:Mentoring
Tech Stack:Cadence ADESpectreVerilog-AVerilogAPythonMATLABCalibreEM/IRAMS verificationMixed mode simulationSignal Integrity

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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