Design Engineer II

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 2-4 yearsEducation: bachelorsSkills: ["Lab instrumentation","Testing","Debugging","Validation","Team mentoring"]

Design Engineer II responsible for post-silicon physical layer electrical validation, focusing on high-speed SERDES protocols, lab instrumentation, and board bring-up. Collaborates on FPGA design and prototyping, with mentoring and potential team leadership responsibilities. Plays a key role in validating IP/SoC physical-layer activities across projects within Cadence’s hardware teams.

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Cadence Design Systems
Cadence Design Systems
7 months ago

Design Engineer II

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Last checked: 13 hours agoStatus: Live

Job Summary

Design Engineer II responsible for post-silicon physical layer electrical validation, focusing on high-speed SERDES protocols, lab instrumentation, and board bring-up. Collaborates on FPGA design and prototyping, with mentoring and potential team leadership responsibilities. Plays a key role in validating IP/SoC physical-layer activities across projects within Cadence’s hardware teams.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Perform post-silicon physical layer electrical validation across multiple SERDES protocols and board bring-up activities
  • •Operate and maintain lab equipment (oscilloscopes, network analyzers, BERT, etc.) to validate signal integrity and performance
  • •Lead or contribute to end-to-end post-silicon validation for at least one full project, including test plan, execution, and issue resolution
  • •Collaborate with FPGA design and PCB teams on schematic/layout considerations and prototyping
  • •Mentor junior engineers and participate in hiring interviews to grow the team

Key Requirements

  • •2-4 years (with Btech) or 1-2 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation
  • •Deep Physical Layer electrical validation experience on at least one high-speed SERDES protocol (PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO)
  • •Hands-on experience with lab equipment such as oscilloscopes, network analyzer, and Bit Error Rate Tester (BERT)
  • •BE/BTech/ME/MTech or equivalent
  • •Experience managing small teams (2+ members) and leading post-silicon validation for at least one full project
Experience:2-4 yearsSemiconductorHardwareElectronicsFPGAPCB
Education:Bachelor's
Skills:Lab instrumentationTestingDebuggingValidationTeam mentoring
Languages:English
Tech Stack:VerilogRTLFPGALabVIEWPythonC/C++TCLASICSoCBoard bring-up

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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