SerDes RTL Design Engineer

AMD
San Jose
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Communication","Analytical skills","Problem-solving","Team player","Willingness to learn"]

Design and implement high-performance, multi-protocol SerDes PHY logic for advanced wireline transceivers. Collaborate with system link architects on RTL micro-architecture, including calibration/adaptation and clock-data-recovery blocks. Apply low-power techniques with PPA analysis, verify functionality via block-level testbenches, and run design checker tooling (LINT/CDC/RDC). Support verification/debug, static timing closure, and pre-tape-out sign-off through silicon bring-up.

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FursaFursa
AMD
AMD
1 day ago

SerDes RTL Design Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 2 hours agoStatus: Live
Reposted: similar role first listed 5 months ago

Job Summary

Design and implement high-performance, multi-protocol SerDes PHY logic for advanced wireline transceivers. Collaborate with system link architects on RTL micro-architecture, including calibration/adaptation and clock-data-recovery blocks. Apply low-power techniques with PPA analysis, verify functionality via block-level testbenches, and run design checker tooling (LINT/CDC/RDC). Support verification/debug, static timing closure, and pre-tape-out sign-off through silicon bring-up.
Location: San Jose
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Collaborate with system link architects to micro-architect high-speed SerDes PHY design.
  • •Develop RTL for digital blocks including calibration/adaptation loops, digital signal processing, and clock-data-recovery.
  • •Apply low-power design techniques and perform PPA analysis.
  • •Verify functionality with block-level test benches; run design checker tools such as LINT/CDC/RDC.
  • •Support functional verification/debug and timing closure; partner with physical design/validation for pre-tape-out sign-off and silicon bring-up.

Key Requirements

  • •Proficiency in logic design concepts and RTL coding using Verilog/SystemVerilog.
  • •Experience with micro-architecture and developing design specifications.
  • •Knowledge of synthesis flow and static timing analysis.
  • •Knowledge of low power design and methodology.
  • •Experience with design checker and/or functional verification tools.
Education:Bachelor's in Electrical engineering, computer engineering, or related field
Skills:CommunicationAnalytical skillsProblem-solvingTeam playerWillingness to learn
Languages:En-us
Tech Stack:RTLVerilogSystemVerilogVerilog/SystemVerilogLINTCDCRDCPPA analysisStatic timing analysisSynthesis flowStatic timing closurePythonPerlTCLScripting languagesLow power designDesign checker toolsFunctional verification tools

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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