IC Design Engineer

Broadcom
India
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 6+ yearsEducation: mastersSkills: ["Analytical skills","Collaboration","Lead by example","Automation mindset"]

Apply and lead Broadcom’s SoC physical design methodology to achieve right-first-time silicon. Drive floorplanning, partitioning, placement, clock tree synthesis, routing, extraction, and physical verification, working toward STA closure. Implement timing and functional ECOs, adapt and build automation flows for reuse, and support top-down/bottom-up physical design integration for 5nm and lower technologies using leading P&R, PV, STA, and ECO EDA tools.

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Broadcom
Broadcom
1 month ago

IC Design Engineer

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Last checked: 13 days agoStatus: Live

Job Summary

Apply and lead Broadcom’s SoC physical design methodology to achieve right-first-time silicon. Drive floorplanning, partitioning, placement, clock tree synthesis, routing, extraction, and physical verification, working toward STA closure. Implement timing and functional ECOs, adapt and build automation flows for reuse, and support top-down/bottom-up physical design integration for 5nm and lower technologies using leading P&R, PV, STA, and ECO EDA tools.
Location: India
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Lead Broadcom’s physical design methodology and milestone flow to achieve right-first-time silicon.
  • •Perform and improve block/level layout activities including floor-planning, partitioning, placement, clock tree synthesis, routing, and physical verification.
  • •Implement timing and functional ECOs and work through P&R, extraction, and physical verification toward STA closure.
  • •Adapt and build automation flows for reuse to improve throughput (TAT) while maintaining quality.
  • •Use and operate appropriate Cadence/Synopsys/Mentor EDA tools for P&R, PV, STA, and ECO; collaborate cross-site/cross-time zone in a multi-functional environment.

Key Requirements

  • •6+ years MSEE/MSCS (8+ years BSEE/BSCS) with a deep understanding of backend digital design flow.
  • •Strong proficiency in floorplanning, partitioning, placement, clock tree synthesis, routing, extraction, and physical verification for SoC top stages.
  • •Working knowledge of timing constraints and physical constraints, with the ability to drive STA closure.
  • •Proficiency in P&R flows and functional/timing ECO implementation, including P&R, PV, and STA stages.
  • •Hands-on expertise with backend EDA tools (Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk) and scripting in Tcl and Perl.
Experience:6+ yearsSoCBackend digital design5nmEDAPhysical designSTAECO
Education:Master's
Skills:Analytical skillsCollaborationLead by exampleAutomation mindset
Tech Stack:CadenceSynopsysMentorEDAGenusInnovusQuantusTempusDCStar-RCXTPTPrimeRailVoltusRedhawkTclPerl

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn