Design Verification Engineer (1-Year Contract)

Join AMD's CIT team as an ASIC Design Verification engineer responsible for developing testbenches, UVM environments, and verification components for cutting-edge IPs. You will write constrained-random and directed tests, analyze coverage, and triage regressions, using Verilog, SystemVerilog, and industry-standard verification methods, across Ottawa, Markham, and Vancouver in a hybrid work setup.