Hardware - Senior SoC Design Engineer

FuriosaAI
Seoul
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 7+ yearsEducation: bachelorsSkills: ["Collaboration","Documentation","Cross-team coordination"]

Own SoC architecture decisions based on requirements and performance targets, then define micro-architecture and implement RTL designs. Lead block/top integration work including timing closure, lint checks, and synthesis, collaborating closely with verification, physical implementation (PnR), and silicon bring-up teams. Use your RTL, integration, and EDA tool experience to support system-level verification and help bring real silicon to production-scale AI compute.

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FursaFursa
FuriosaAI
FuriosaAI
2 weeks ago

Hardware - Senior SoC Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 55 minutes agoStatus: Live

Job Summary

Own SoC architecture decisions based on requirements and performance targets, then define micro-architecture and implement RTL designs. Lead block/top integration work including timing closure, lint checks, and synthesis, collaborating closely with verification, physical implementation (PnR), and silicon bring-up teams. Use your RTL, integration, and EDA tool experience to support system-level verification and help bring real silicon to production-scale AI compute.
Location: Seoul
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Determine optimal SoC architecture based on requirements, target performance, and system specifications.
  • •Define micro-architecture and implement corresponding RTL designs.
  • •Perform subsystem/block-top integration, including timing closure, lint checks, and synthesis; collaborate with other teams.
  • •Collaborate with the Design Verification team to develop verification plans and achieve coverage goals.
  • •Collaborate with Physical Implementation (PnR) and Silicon bring-up teams to anticipate issues and support system-level verification.

Key Requirements

  • •Bachelor’s degree in Electrical Engineering or Computer Engineering (or Master’s degree with 5+ years of RTL design experience).
  • •7+ years of RTL design experience (5+ years with a Master’s degree).
  • •Experience with SoC system IP design and practical System/Chip-top level integration.
  • •Experience designing subsystems/top-level blocks.
  • •Strong understanding of AMBA bus protocol and bus interfaces, including clock domain crossing.
Experience:7+ years
Education:Bachelor's in Electrical Engineering or Computer Engineering
Skills:CollaborationDocumentationCross-team coordination
Languages:Korean
Tech Stack:SoCRTLMicro-ArchitectureRTL designTiming closureLint checkSynthesisSubsystem integrationTop-level integrationPnRSilicon bring-upSystem level verificationFPGA portingAMBABus interfacesClock Domain Crossing (CDC)Design automationScriptingEDA toolsPower estimation

Company Brief

FuriosaAI
Designs and develops data‑center AI inference accelerators (RNGD) and a full stack hardware‑software platform to deliver energy‑efficient, high‑performance AI compute for enterprise and cloud customers.
Industry: Hardware Devices
Company Size: Medium (51 to 250 employees)
Growth: Scaleup
Valuation: USD 500M to 1B
Funding: Series C
Headquarters: Seoul, South Korea
Founded: 2017
Glassdoor
Glassdoor: 4.6
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