Pre-si Verification Engineer

Join the compute die frontend design and verification team for next-generation Client SoCs, ensuring functional correctness and quality before silicon tape-out. Build and maintain SystemVerilog/UVM verification environments, create constrained-random and directed tests, and run simulation/emulation to validate functionality, power, and performance. Own debug and root-cause analysis of RTL and testbench failures, drive coverage closure, and collaborate across architecture, RTL, post-silicon, and validation teams.