Senior Static Timing Analysis (STA) Engineer

Intel
Phoenix, Santa Clara
Workplace: HybridFull timeUSD 164,470 - 269,100 annuallyFunction: Solutions Engineering & Sales EngineeringExperience: 6+ yearsEducation: bachelorsSkills: ["Technical leadership","Ownership","Strategic problem-solving","Cross-functional collaboration","Communication excellence"]

Lead SOC-level static timing analysis to ensure next-generation semiconductor designs meet functional and performance requirements. Optimize timing constraints, roll up timing across chip or blocks, and develop high-quality timing models. Define PVT conditions aligned with product plans and support efficient physical design execution by working closely with architecture, logic, clocking, DFT, and full-chip teams. Contribute to tools, flows, and methodologies that improve SoC timing and physical design processes.

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Intel
Intel
4 days ago

Senior Static Timing Analysis (STA) Engineer

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Last checked: 12 hours agoStatus: Live

Job Summary

Lead SOC-level static timing analysis to ensure next-generation semiconductor designs meet functional and performance requirements. Optimize timing constraints, roll up timing across chip or blocks, and develop high-quality timing models. Define PVT conditions aligned with product plans and support efficient physical design execution by working closely with architecture, logic, clocking, DFT, and full-chip teams. Contribute to tools, flows, and methodologies that improve SoC timing and physical design processes.
Location: Phoenix, Santa Clara
Workplace: Hybrid
Employment Type: Full time
Job Function: Solutions Engineering & Sales Engineering
Seniority: Mid level

Key Responsibilities

  • •Perform SOC level timing analysis and optimization to ensure designs meet functional and performance requirements.
  • •Generate and verify timing constraints and address timing violations at the chip or block level for SoCs.
  • •Conduct timing rollups and develop optimized clock networks focused on functionality, performance, and power efficiency.
  • •Define methodologies to produce high-quality timing models and enable efficient physical design execution under PVT conditions.
  • •Collaborate with clocking, architecture, logic design, DFT, and physical design teams to balance timing fixes with power delivery and validate clock network guidelines.

Pay and Benefits

Salary: USD 164,470 - 269,100 annually
Equity and Bonus:Equity
Perks:Health InsuranceRetirementPaid Leave

Key Requirements

  • •Bachelor’s degree in Computer Engineering, Computer Science, or related STEM with 6+ years of industry experience; or a Master’s degree with 4+ years of experience.
  • •5+ years of SOC level static timing analysis experience, including clock network design and timing closure methodologies.
  • •Experience adapting timing constraints, understanding physical design, and using optimization techniques to address timing violations.
  • •Hands-on experience with industry-standard tools for timing analysis, extraction, and physical design.
  • •Experience with TCL scripting and timing budgeting processes.
Experience:6+ years
Education:Bachelor's in Computer Engineering, Computer Science, or related STEM discipline
Skills:Technical leadershipOwnershipStrategic problem-solvingCross-functional collaborationCommunication excellence
Tech Stack:SOC level static timing analysisClock network designTiming closureTiming constraintsTiming rollupsSignal integrityPVT conditionsPhysical designDFTTCL scriptingTiming budgeting

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
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