STA Engineer

AMD
Bengaluru
Workplace: OnsiteFull timeINR 3,338,160 - 4,768,800 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 8+ yearsEducation: bachelorsSkills: []

Develop complex multi-mode/multi-corner timing constraints compatible with RTL and signoff, ensuring high-quality SDC using industry EDA tools. Execute pre-route timing checks and QoR cleanup to remove SDC issues and deliver clean STA handoffs. Lead timing closure for sub-chip, subsystem, or full-chip, including interface timing and DRV closure. Generate and drive timing ECOs using tools like DMSA/Tweaker and support timing analysis using Synopsys/other tool flows.

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FursaFursa
AMD
AMD
1 day ago

STA Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 2 hours agoStatus: Live
Reposted: similar role first listed 3 months ago

Job Summary

Develop complex multi-mode/multi-corner timing constraints compatible with RTL and signoff, ensuring high-quality SDC using industry EDA tools. Execute pre-route timing checks and QoR cleanup to remove SDC issues and deliver clean STA handoffs. Lead timing closure for sub-chip, subsystem, or full-chip, including interface timing and DRV closure. Generate and drive timing ECOs using tools like DMSA/Tweaker and support timing analysis using Synopsys/other tool flows.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Develop timing constraints for complex multi-mode/multi-corner scenarios compatible with RTL and signoff.
  • •Ensure constraints quality (SDC) using industry tools and well-established corner/timing signoff methodology.
  • •Drive pre-route timing checks and QoR cleanup to eliminate SDC issues and enable quality STA handoff.
  • •Own timing closure for one or more sub-chip/subsystem or full-chip, including interface timing closure and DRV closure.
  • •Generate timing ECOs using tools like DMSA/Tweaker and lead subsystem/subchip/full-chip timing closure efforts.

Pay and Benefits

Salary: INR 3,338,160 - 4,768,800 annually

Key Requirements

  • •8+ years building timing constraints for IPs, blocks, and full-chip implementation in flat/hierarchical flows.
  • •Analyze timing reports to identify design and constraints-related issues affecting timing closure.
  • •Strong EDA timing tool experience (e.g., Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker).
  • •Proficiency with SDC constraints and signoff timing concepts such as OCV/AOCV/POCV and DFT modes requirements.
  • •Strong TCL/scripting capability and timing eco/physical design ECO understanding.
Experience:8+ yearsSemiconductorEDATiming signoffPhysical design
Education:Bachelor's in computer engineering/Electrical Engineering
Languages:En-us
Tech Stack:SDCFishtailGCASynopsys Design CompilerPrimetimeSpyglassTweakerDMSATclLinuxECOOCVAOCVPOCVDFTInterface timingTiming closure

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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