ASIC Design and STA Engineer

Own full-chip and/or chiplet-level STA convergence from early stages through signoff for NVIDIA’s Networking Silicon team. Contribute to top-level floorplan and clock planning, optimize timing with CAD signoff flows, and integrate digital partitions with analog IP timing. Partner with logic design and DFT engineers to define and implement constraints across work modes, driving convergence optimized for runtime and efficiency.