DFT - ATPG

AMD
Bengaluru
Workplace: HybridFull timeINR 3,338,160 - 4,768,800 annuallyFunction: Design (Product/UX/UI/Visual)Education: mastersSkills: ["Detail-oriented","Communication","Problem-solving","Accuracy","Test coverage analysis"]

Join the Radeon Technologies Group front-end design/integration team to drive first-pass silicon success. Implement and verify DFT architecture and features, generate and verify scan insertion/ATPG patterns using gate-level simulation, and analyze test coverage and test cost reduction. Provide post-silicon support to improve bring-up and enhance yield learning while coordinating closely with architecture, IP design, physical design, and product engineering teams.

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FursaFursa
AMD
AMD
3 days ago

DFT - ATPG

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Source: Company careers pageValidated by: Fursa AI
Last checked: 2 hours agoStatus: Live

Job Summary

Join the Radeon Technologies Group front-end design/integration team to drive first-pass silicon success. Implement and verify DFT architecture and features, generate and verify scan insertion/ATPG patterns using gate-level simulation, and analyze test coverage and test cost reduction. Provide post-silicon support to improve bring-up and enhance yield learning while coordinating closely with architecture, IP design, physical design, and product engineering teams.
Location: Bengaluru
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Implement and verify DFT architecture and features for silicon design.
  • •Generate ATPG patterns, including scan insertion and ATPG pattern generation.
  • •Verify ATPG patterns with gate-level simulation.
  • •Analyze test coverage and perform test cost reduction.
  • •Provide post-silicon support to ensure successful bring-up and improve yield learning.

Pay and Benefits

Salary: INR 3,338,160 - 4,768,800 annually

Key Requirements

  • •Understanding of Design for Test (DFT) methodologies and DFT verification experience (e.g., IEEE1500, JTAG 1149.x, Scan, memory BIST).
  • •Experience with Mentor testkompress and/or Synopsys Tetramax / DFTMAX.
  • •Experience with VCS simulation tool and Verilog RTL design.
  • •Ability to implement and verify DFT architecture and features, including scan insertion and ATPG pattern generation.
  • •Bachelors or Masters degree in computer engineering or electrical engineering.
Education:Master's
Skills:Detail-orientedCommunicationProblem-solvingAccuracyTest coverage analysis
Tech Stack:DFTATPGIEEE1500JTAG 1149.xScanMemory BISTMentor testkompressSynopsys TetramaxDFTMAXVCSPerlShellVerilog RTLGate-level simulation

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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