Design Verification Engineer (Silicon Engineering)

Develop and execute digital ASIC verification at block and system level for space and ground infrastructure. Write and review test plans, build SystemVerilog testbench infrastructure (UVM and non-UVM), run regressions, and close code and functional coverage. Automate test generation using Python and MATLAB, and support pre-silicon verification, chip bring-up, and post-silicon validation while collaborating with cross-disciplinary engineering teams.