Silicon Verification Engineer

AMD
Singapore
Workplace: HybridFull timeFunction: QA, Test & Release EngineeringEducation: bachelorsSkills: ["Analytical","Debugging","Communication","Problem-solving","Collaboration"]

Join the DDR PHY IP development team as an entry-level Silicon Verification Engineer. You’ll build and maintain UVM-based verification environments, write and run directed and constrained-random tests with functional coverage, and debug simulation failures with RTL designers. The role includes creating verification collateral, running regressions, tracking coverage closure, and contributing automation scripts to improve verification efficiency, supporting reliable silicon for SoCs across data center, mobile, and automotive.

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FursaFursa
AMD
AMD
1 month ago

Silicon Verification Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 13 hours agoStatus: Live

Job Summary

Join the DDR PHY IP development team as an entry-level Silicon Verification Engineer. You’ll build and maintain UVM-based verification environments, write and run directed and constrained-random tests with functional coverage, and debug simulation failures with RTL designers. The role includes creating verification collateral, running regressions, tracking coverage closure, and contributing automation scripts to improve verification efficiency, supporting reliable silicon for SoCs across data center, mobile, and automotive.
Location: Singapore
Workplace: Hybrid
Employment Type: Full time
Job Function: QA, Test & Release Engineering
Seniority: Entry level

Key Responsibilities

  • •Develop and maintain UVM-based verification environments for DDR PHY IP.
  • •Write and execute test plans, including directed and constrained-random tests, along with functional coverage models.
  • •Debug simulation failures by analyzing waveforms and working with RTL designers to resolve issues.
  • •Create and maintain verification collateral such as testbenches, checkers, and scoreboards.
  • •Run regressions, track functional coverage, and ensure design verification closure while contributing automation for efficiency improvements.

Key Requirements

  • •Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • •Strong understanding of digital design fundamentals, including clocking and timing.
  • •Experience with SystemVerilog and UVM (academic or internship exposure preferred).
  • •Familiarity with simulation tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa.
  • •Proficiency in scripting languages (Python, Perl, or TCL) for automation.
Education:Bachelor's in Electrical Engineering, Computer Engineering, or related field
Skills:AnalyticalDebuggingCommunicationProblem-solvingCollaboration
Languages:En-us
Tech Stack:DDR PHY IPDDR memory protocolsUVMSystemVerilogRTLSynopsys VCSCadence XceliumMentor QuestaPythonPerlTCLDirected testsConstrained-random testsFunctional coverageRegression

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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