Texas Instruments

3 months ago

Senior Layout Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 13 hours agoStatus: Live

Job Summary

Own full-chip analog/mixed-signal layout execution from definition through release to production, coordinating across design, packaging, and process teams to balance area, performance, and schedule. Lead layout planning, risk mitigation, and final layout sign-off against checklists while performing verification closure (LVS/DRC/ERC, antenna debug, and layout parasitics). Update PDK/P-cell and design rules, mentor junior layout engineers, and develop test vehicles for new process/package technologies.

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Solutions Engineering & Sales Engineering

Seniority: Mid level

Key Responsibilities

•Frame layout schedules, effort estimation, and risk/mitigation plans for layout activities across the project’s layout engineers.
•Collaborate with designers to understand IC architecture and key requirements, and coordinate with design, packaging, and process teams to balance area, performance, and schedule.
•Work with process development to carry out PDK, P-cell, and design rule updates, and with packaging to develop custom lead-frames for packages.
•Perform analysis and closure of electro-migration, thermal gradients, ESD/LU performance, and layout parasitics; ensure final layout meets design expectations and layout checklists.
•Mentor and guide junior/contract layout engineers, review their work, and identify process/quality/cycle-time improvements; develop test vehicles for new process/package technology development.

Key Requirements

•3–10 years of experience in full-chip layout from definition through release to production.
•Strong analog and mixed-signal layout techniques, including device matching, power bus design, cross-talk avoidance, and ESD/LU protection techniques.
•Strong verification and debug skills including LVS, DRC, ERC, antenna debug, and understanding of layout parasitics (R, C, diodes, BJTs).
•Experience with semiconductor device physics and semiconductor fabrication process, including technologies such as 40nm, 65nm, 90nm, 130nm, 180nm, BiCMOS, or BCD.
•Proficiency with tools such as Virtuoso XL, Assura, PVS, and Voltas, with ability to ramp up on new tools/process and mentor layout engineers.

Experience:3-10 yearsSemiconductorsIC layoutAnalogMixed-signal

Education:Bachelor's

Skills:TeamworkCommunicationProblem-solvingDocumentationTime management

Languages:English

Tech Stack:Virtuoso XLAssuraPVSVoltasSKILLLVSDRCERC

Company Brief

Texas Instruments

Designs and manufactures semiconductors and analog chips used in industrial, automotive, personal electronics, communications, and enterprise systems. It is one of the world’s largest semiconductor companies, with a broad portfolio of embedded processing and power products.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Dallas, United States

Founded: 1930

Website LinkedIn

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Texas Instruments

3 months ago

Senior Layout Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 13 hours agoStatus: Live

Job Summary

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Solutions Engineering & Sales Engineering

Seniority: Mid level

Key Responsibilities

•Frame layout schedules, effort estimation, and risk/mitigation plans for layout activities across the project’s layout engineers.
•Collaborate with designers to understand IC architecture and key requirements, and coordinate with design, packaging, and process teams to balance area, performance, and schedule.
•Work with process development to carry out PDK, P-cell, and design rule updates, and with packaging to develop custom lead-frames for packages.
•Perform analysis and closure of electro-migration, thermal gradients, ESD/LU performance, and layout parasitics; ensure final layout meets design expectations and layout checklists.
•Mentor and guide junior/contract layout engineers, review their work, and identify process/quality/cycle-time improvements; develop test vehicles for new process/package technology development.

Key Requirements

•3–10 years of experience in full-chip layout from definition through release to production.
•Strong analog and mixed-signal layout techniques, including device matching, power bus design, cross-talk avoidance, and ESD/LU protection techniques.
•Strong verification and debug skills including LVS, DRC, ERC, antenna debug, and understanding of layout parasitics (R, C, diodes, BJTs).
•Experience with semiconductor device physics and semiconductor fabrication process, including technologies such as 40nm, 65nm, 90nm, 130nm, 180nm, BiCMOS, or BCD.
•Proficiency with tools such as Virtuoso XL, Assura, PVS, and Voltas, with ability to ramp up on new tools/process and mentor layout engineers.

Experience:3-10 yearsSemiconductorsIC layoutAnalogMixed-signal

Education:Bachelor's

Skills:TeamworkCommunicationProblem-solvingDocumentationTime management

Languages:English

Tech Stack:Virtuoso XLAssuraPVSVoltasSKILLLVSDRCERC

Company Brief

Texas Instruments

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Dallas, United States

Founded: 1930

Website LinkedIn