SpaceX

1 month ago

Sr. ASIC DFT Engineer (Silicon)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 4 hours agoStatus: Live

Job Summary

Senior ASIC DFT Engineer developing and optimizing design-for-test architectures for space-grade ASICs used in Starlink. You will implement DFT/IP integrations, run ATPG and pattern generation, verify simulations, and collaborate with cross-functional teams to ensure robust post-silicon bring-up and test capabilities across multiple SpaceX silicon programs.

Location: Austin, Irvine, Sunnyvale

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Seniority: Sr. Manager level

Key Responsibilities

•Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools
•Integration and verification of Design for Test (DFT) IPs and fabrics within Subsystems
•Set up and run Automatic Test Pattern Generation (ATPG) tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows
•Run and debug non-timing and SDF annotated gate-level simulations
•Create and validate DFT patterns for post-silicon bringup and also help with ATE debug through all cycles of silicon characterization

Key Requirements

•Bachelor's degree in electrical engineering, computer engineering, or physics
•5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing
•Experience with Automated Test Equipment (ATE) platforms (e.g., Teradyne, Advantest) for high-volume manufacturing test development and debug
•Experience collaborating with cross-functional teams to ensure DFT features meet production requirements, utilizing Siemens Tessent workflows
•Knowledge of industry standards for testability (e.g., IEEE 1500, 1687) and experience with low-power DFT techniques using Siemens Tessent

Experience:5+ yearsSpaceAerospaceSemiconductorsTelecommunications

Education:Bachelor's

Skills:Problem-solvingCommunicationTeamwork

Languages:English

Tech Stack:Siemens TessentATPGPerlPythonTclC++SDFGate-level simulationsDFTTestabilityIEEE 1500IEEE 1687

Company Brief

SpaceX

Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.

Industry: Aerospace Manufacturing

Company Size: Enterprise (1,001+ employees)

Growth: Established Company

Valuation: Hectocorn (USD 100B+)

Funding: Series E+

Headquarters: Hawthorne, United States

Founded: 2002

Glassdoor: 4.2

Website LinkedIn

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SpaceX

1 month ago

Sr. ASIC DFT Engineer (Silicon)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 4 hours agoStatus: Live

Job Summary

Location: Austin, Irvine, Sunnyvale

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Seniority: Sr. Manager level

Key Responsibilities

•Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools
•Integration and verification of Design for Test (DFT) IPs and fabrics within Subsystems
•Set up and run Automatic Test Pattern Generation (ATPG) tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows
•Run and debug non-timing and SDF annotated gate-level simulations
•Create and validate DFT patterns for post-silicon bringup and also help with ATE debug through all cycles of silicon characterization

Key Requirements

•Bachelor's degree in electrical engineering, computer engineering, or physics
•5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing
•Experience with Automated Test Equipment (ATE) platforms (e.g., Teradyne, Advantest) for high-volume manufacturing test development and debug
•Experience collaborating with cross-functional teams to ensure DFT features meet production requirements, utilizing Siemens Tessent workflows
•Knowledge of industry standards for testability (e.g., IEEE 1500, 1687) and experience with low-power DFT techniques using Siemens Tessent

Experience:5+ yearsSpaceAerospaceSemiconductorsTelecommunications

Education:Bachelor's

Skills:Problem-solvingCommunicationTeamwork

Languages:English

Tech Stack:Siemens TessentATPGPerlPythonTclC++SDFGate-level simulationsDFTTestabilityIEEE 1500IEEE 1687

Company Brief

SpaceX

Industry: Aerospace Manufacturing

Company Size: Enterprise (1,001+ employees)

Growth: Established Company

Valuation: Hectocorn (USD 100B+)

Funding: Series E+

Headquarters: Hawthorne, United States

Founded: 2002

Glassdoor: 4.2

Website LinkedIn