Design Verification Manager

Texas Instruments
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 8-12 yearsEducation: bachelorsSkills: ["Debugging","Problem-solving","Communication","Interpersonal","Analytical skills"]

Lead end-to-end design verification for IP/subsystems/SoCs, owning spec-to-regression traceability and driving DV closure through post-silicon. Collaborate with architecture during specification, define verification strategy and signoff metrics, and manage the DV environment (test benches, UVC integration, checkers and coverage). Verify functional and firmware scenarios across RTL/PARTL and GLS/PAGLS modes using AMS, CDC, and formal techniques, while supporting customer debugging and ISO 26262/ISO 21434 processes.

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FursaFursa
Texas Instruments
Texas Instruments
6 months ago

Design Verification Manager

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Source: Company careers pageValidated by: Fursa AI
Last checked: 15 hours agoStatus: Live

Job Summary

Lead end-to-end design verification for IP/subsystems/SoCs, owning spec-to-regression traceability and driving DV closure through post-silicon. Collaborate with architecture during specification, define verification strategy and signoff metrics, and manage the DV environment (test benches, UVC integration, checkers and coverage). Verify functional and firmware scenarios across RTL/PARTL and GLS/PAGLS modes using AMS, CDC, and formal techniques, while supporting customer debugging and ISO 26262/ISO 21434 processes.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Manager level

Key Responsibilities

  • •Own end-to-end IP/subsystem/SoC DV and post-silicon debugs, from spec definition through verification closure and customer issue resolution.
  • •Collaborate with architecture during specification and define the verification strategy with 100% spec-to-regression traceability and signoff metrics.
  • •Conduct IP/subsystem/SoC verification for functional and firmware scenarios in RTL/PARTL and GLS/PAGLS modes.
  • •Own and evolve the DV environment: define/develop test benches, enhance UVC integration, update checkers and coverage monitors, and adapt DV flow.
  • •Provide SoC DV signoff based on regression and coverage metrics, participate in customer reviews/certification processes, and ensure adherence to ISO 26262/ISO 21434.

Key Requirements

  • •Bachelor’s or Master’s degree in EE/EC/EI/CS or related specializations.
  • •8-12 years of relevant experience.
  • •Experience in C-based SoC design verification (DV) with firmware verification exposure and deep knowledge of UVM/SystemVerilog, Specman, and GLS/PAGLS/UPF-based verification.
  • •Proficiency in scripting (Perl, Python) and knowledge of AI/ML-based DV.
  • •In-depth understanding of protocols including AHB, CAN, I2C, SPI, UART, and USB, plus strong debugging skills with Verilog and VHDL.
Experience:8-12 yearsSystem-on-chip (SoC)Design verification (DV)
Education:Bachelor's in EE/EC/EI/CS (or related specializations)
Skills:DebuggingProblem-solvingCommunicationInterpersonalAnalytical skills
Languages:US
Tech Stack:CSystem-on-Chip (SoC)UVMSystemVerilogSpecmanGLSPAGLSUPFPerlPythonAI/MLAHBCANI2CSPIUARTUSBARMPower-aware simulationsVerilog

Company Brief

Texas Instruments
Designs and manufactures semiconductors and analog chips used in industrial, automotive, personal electronics, communications, and enterprise systems. It is one of the world’s largest semiconductor companies, with a broad portfolio of embedded processing and power products.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Dallas, United States
Founded: 1930
WebsiteLinkedIn