Design Verification Manager

Lead end-to-end design verification for IP/subsystems/SoCs, owning spec-to-regression traceability and driving DV closure through post-silicon. Collaborate with architecture during specification, define verification strategy and signoff metrics, and manage the DV environment (test benches, UVC integration, checkers and coverage). Verify functional and firmware scenarios across RTL/PARTL and GLS/PAGLS modes using AMS, CDC, and formal techniques, while supporting customer debugging and ISO 26262/ISO 21434 processes.