Principal Design Engineer

Cadence Design Systems
Austin
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 12+ yearsEducation: bachelorsSkills: ["Communication","Cross-functional collaboration","Innovation","Automation"]

Design and integrate IPs in SoC based on customer architectural specifications, ensuring quality through Lint/CDC checks and resolving issues. Create synthesis constraints and microarchitectural specification documents, performing basic synthesis for PPA optimization. Support verification and physical design teams with test planning, coverage analysis, feature debugging, and implementation. Automate repetitive workflows with innovative scripting and collaborate across teams to deliver projects.

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Cadence Design Systems
Cadence Design Systems
3 days ago

Principal Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 3 hours agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Design and integrate IPs in SoC based on customer architectural specifications, ensuring quality through Lint/CDC checks and resolving issues. Create synthesis constraints and microarchitectural specification documents, performing basic synthesis for PPA optimization. Support verification and physical design teams with test planning, coverage analysis, feature debugging, and implementation. Automate repetitive workflows with innovative scripting and collaborate across teams to deliver projects.
Location: Austin
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Design and integrate IPs in SoC based on customer high-level architectural specifications.
  • •Perform Lint/CDC checks for quality assurance and resolve related issues.
  • •Create synthesis constraints and perform basic synthesis for PPA optimization.
  • •Create detailed microarchitectural specification documents for the design.
  • •Support verification and physical design teams with test plan creation, coverage analysis, feature debugging, and design implementation as needed.

Key Requirements

  • •B.E./B.Tech/M.Tech with 12+ years of experience as a digital design engineer.
  • •Strong digital design fundamentals and proficiency in Verilog/SystemVerilog (SV).
  • •Solid knowledge of Lint/CDC tools, including setting up flows from scratch.
  • •Knowledge of creating synthesis constraints and Static Timing Analysis (STA), with synthesis tools familiarity a plus.
  • •Experience with scripting languages (Python/Perl/Tcl) and automation for repetitive tasks.
Experience:12+ yearsDigital design
Education:Bachelor's
Skills:CommunicationCross-functional collaborationInnovationAutomation
Tech Stack:VerilogSystemVerilogLintCDCStatic Timing Analysis (STA)Synthesis constraintsSynthesisXceliumVerisiumPythonPerlTclAMBA protocolsPCIeEthernetDDR

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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Glassdoor: 3.9
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