ASIC Design Verification Engineer | UVM | Exp 8+ Years
Cisco
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 7+ yearsEducation: bachelorsSkills: ["SystemVerilog","UVM","Verilog","Test benches","Perl","Python","Gate Level Simulations","RTL verification"]Design and verify ASICs and subsystems for Cisco platforms using UVM, building DV benches, and leading bring-up activities. Collaborate with designers, architects, and software teams to ensure RTL quality and complete verification coverage across block, cluster, and top levels. Drive DV infrastructure, test plans, and enablement from scratch and through post-silicon bring-up.
