ASIC Engineering Technical Leader - Emulation

Cisco
San Jose
Workplace: OnsiteFull timeUSD 186,900 - 267,700 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 10+ yearsSkills: ["Technical leadership","Mentoring","Communication","Collaboration","Root cause analysis"]

Lead the planning and execution of ASIC verification for complex networking SoCs, driving verification strategy, testplan development, coverage closure, and end-to-end execution across multiple IPs and subsystems. Provide technical leadership and mentorship to verification engineers while building scalable, reusable verification environments using SystemVerilog/UVM. Partner with architecture, RTL, emulation, FPGA, and post-silicon teams to enable efficient debug, root-cause analysis, and successful silicon bring-up.

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FursaFursa
Cisco
Cisco
5 days ago

ASIC Engineering Technical Leader - Emulation

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Source: Company careers pageValidated by: Fursa AI
Last checked: 2 hours agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Lead the planning and execution of ASIC verification for complex networking SoCs, driving verification strategy, testplan development, coverage closure, and end-to-end execution across multiple IPs and subsystems. Provide technical leadership and mentorship to verification engineers while building scalable, reusable verification environments using SystemVerilog/UVM. Partner with architecture, RTL, emulation, FPGA, and post-silicon teams to enable efficient debug, root-cause analysis, and successful silicon bring-up.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Sr. Manager level

Key Responsibilities

  • •Lead planning and execution of ASIC verification for complex networking SoCs to ensure quality and predictable project execution.
  • •Drive verification strategy, testplan development, coverage closure, and multi-IP/subsystem verification execution.
  • •Provide technical leadership and mentorship to verification engineers, promoting best practices and technical excellence.
  • •Develop and enhance scalable, reusable verification environments, infrastructure, and methodologies using SystemVerilog/UVM.
  • •Collaborate across architecture, RTL, emulation, FPGA, and post-silicon teams to enable efficient debug, root-cause analysis, and silicon bring-up.

Pay and Benefits

Salary: USD 186,900 - 267,700 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kPaid ParentalDisability CoverageLife InsuranceEquityPaid HolidaysPaid Leave

Key Requirements

  • •Bachelor's with 10+ years, or Master's with 7+ years, or Ph.D. with 5+ years of related experience in ASIC/SoC verification.
  • •Strong experience with SystemVerilog and UVM, including hardware emulation and modern verification methodologies.
  • •Experience developing and executing verification strategies for complex ASIC or SoC programs.
  • •Experience leading verification teams or serving as the technical lead for complex verification projects.
  • •Proficiency in scripting languages such as Python or Perl.
Experience:10+ years
Skills:Technical leadershipMentoringCommunicationCollaborationRoot cause analysis
Tech Stack:SystemVerilogUVMPythonPerlHardware emulationFPGA prototypingCadence PalladiumSiemens VeloceSiemens StratoCSSynopsys ZeBuPCIeEthernetCXLHBMDDR

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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