Silicon Design Verification Engineer

AMD
Markham
Workplace: HybridFull timeCAD 92,400 - 158,400 annuallyFunction: Design (Product/UX/UI/Visual)Education: mastersSkills: ["Communication","Analytical skills","Problem-solving","Teamwork","Willingness to learn"]

Own verification activities in the AMD SoC Verification Team, partnering with senior verification and RTL engineers to design UVM/SystemVerilog testbenches and build efficient constrained-random and/or directed verification environments. Develop and enhance coverage and quality metrics, use SVA and formal tools to verify designs, debug issues to close functional coverage, and support performance and power-aware verification efforts.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
AMD
AMD
1 day ago

Silicon Design Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live

Job Summary

Own verification activities in the AMD SoC Verification Team, partnering with senior verification and RTL engineers to design UVM/SystemVerilog testbenches and build efficient constrained-random and/or directed verification environments. Develop and enhance coverage and quality metrics, use SVA and formal tools to verify designs, debug issues to close functional coverage, and support performance and power-aware verification efforts.
Location: Markham
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Work in the AMD SoC Verification Team on block-level and sub-system level verification activities.
  • •Design UVM/SystemVerilog testbenches and verification environments to efficiently verify designs.
  • •Create and enhance constrained-random and/or directed verification environments and improve coverage.
  • •Debug tests with design engineers to ensure functionally correct design blocks and close coverage.
  • •Coordinate with RTL engineers for logic design improvements (including clock gating) and track verification quality metrics (pass rates, code and functional coverage).

Pay and Benefits

Salary: CAD 92,400 - 158,400 annually

Key Requirements

  • •Create test plans for complex IP designs in collaboration with senior verification engineers.
  • •Design and implement verification testbenches using SystemVerilog and UVM.
  • •Use SystemVerilog Assertions (SVA) and industry formal tools to formally verify designs.
  • •Develop constrained-random and/or directed verification environments and close coverage using verification quality metrics.
  • •Have project-level understanding of RTL implementation and computer organization/digital logic fundamentals, with programming knowledge (SystemVerilog/C++ and Python automation as a plus).
Experience:Processor architectureDigital designVerificationRTL implementation
Education:Master's in Computer Engineering or Electrical Engineering
Skills:CommunicationAnalytical skillsProblem-solvingTeamworkWillingness to learn
Tech Stack:UVMSystemVerilogSystem Verilog Assertions (SVA)Constrained-random verificationDirected verificationFormal verificationPythonC++RTLClock gatingSVAPCIEPCIeAMBA AXIAMBA AXI protocol

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn