ASIC Physical Design Engineer - 7 to 10 years - Pune

Cisco
Pune
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 7-10 yearsEducation: bachelorsSkills: ["Teamwork","Analytical thinking","Problem-solving","Debugging","Collaboration"]

Work on the physical implementation of Cisco silicon photonics driver integrated circuits, supporting next-generation 100G/200G/400G-per-lambda optical interconnect solutions. You’ll own block-level implementation through RTL/netlist-to-GDSII, contribute to top-level floorplanning, and drive place-and-route, clock/power distribution, STA, ECOs, and physical verification to achieve timing, power, area, congestion, and signoff closure for successful silicon delivery.

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Cisco
Cisco
1 month ago

ASIC Physical Design Engineer - 7 to 10 years - Pune

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Job Summary

Work on the physical implementation of Cisco silicon photonics driver integrated circuits, supporting next-generation 100G/200G/400G-per-lambda optical interconnect solutions. You’ll own block-level implementation through RTL/netlist-to-GDSII, contribute to top-level floorplanning, and drive place-and-route, clock/power distribution, STA, ECOs, and physical verification to achieve timing, power, area, congestion, and signoff closure for successful silicon delivery.
Location: Pune
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Own block-level RTL/netlist-to-GDSII implementation and support full-chip designs in advanced technology nodes.
  • •Drive digital implementation work including hierarchical floorplans, macro placement, I/O planning, congestion, timing, and power distribution.
  • •Run static timing analysis, interpret timing reports, and implement timing ECOs using tools such as Tempus/Tempus ECO (or equivalent).
  • •Collaborate cross-functionally (RTL, Analog, DFT, Packaging, CAD, EDA) to resolve implementation issues and improve design convergence.
  • •Perform back-end signoff checks (power integrity, IR/EM analysis, and physical verification) and develop automation scripts to improve QoR tracking and flow efficiency.

Key Requirements

  • •Bachelor’s degree in Electrical Engineering or related field (Master’s preferred).
  • •8-12 years of ASIC/SoC physical design (PD) and implementation experience in advanced technology nodes.
  • •Hands-on experience with full physical design flow: floor planning, power planning, place & route, clock tree synthesis, extraction, STA, ECOs, and physical signoff.
  • •Experience with industry-standard EDA tools (e.g., Cadence Genus, Cadence Innovus, Cadence Tempus/Synopsys PrimeTime, Cadence Voltus/Ansys RedHawk, Siemens Calibre/Cadence Pegasus).
  • •Strong scripting skills in TCL, Python, or Perl and ability to collaborate across RTL, Analog, DFT, Packaging, CAD, and EDA teams.
Experience:7-10 yearsASICSoCSilicon photonicsOptical interconnectsAdvanced CMOS
Education:Bachelor's in Electrical Engineering
Skills:TeamworkAnalytical thinkingProblem-solvingDebuggingCollaboration
Tech Stack:TCLPythonBashPerlCadence GenusCadence InnovusCadence TempusSynopsys PrimeTimeCadence VoltusAnsys RedHawkSiemens CalibreCadence PegasusRTLNetlistGDSIISTAECOIR analysisPower integrityPlace and route

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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