Lead Design Engineer

Cadence Design Systems
Austin
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: mastersSkills: ["Communication","Cross-functional collaboration","Automation","Problem-solving","Quality assurance"]

Design and integrate IPs for SoC using customer architectural specifications, driving quality through Lint/CDC checks and resolving issues. Create synthesis constraints and perform basic PPA optimization, while writing microarchitectural specification documents. Partner with verification to support test planning, coverage analysis, and feature debugging, and assist physical design as needed. Automate repetitive workflows and collaborate across teams to deliver project outcomes.

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Cadence Design Systems
Cadence Design Systems
3 days ago

Lead Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 3 hours agoStatus: Live

Job Summary

Design and integrate IPs for SoC using customer architectural specifications, driving quality through Lint/CDC checks and resolving issues. Create synthesis constraints and perform basic PPA optimization, while writing microarchitectural specification documents. Partner with verification to support test planning, coverage analysis, and feature debugging, and assist physical design as needed. Automate repetitive workflows and collaborate across teams to deliver project outcomes.
Location: Austin
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Design and integrate IPs in SoC based on customer high-level architectural specifications.
  • •Perform Lint/CDC checks and resolve related quality issues.
  • •Create synthesis constraints at IP and SoC level and run basic synthesis for PPA optimization.
  • •Write detailed microarchitectural specification documents for the design.
  • •Support verification for test plan creation, coverage analysis, feature debugging, and physical design implementation as needed.

Key Requirements

  • •B.E./B.Tech/M.Tech with at least 5 years of experience as a digital design engineer.
  • •Strong digital design fundamentals and Verilog/SystemVerilog (SV).
  • •Solid experience with Lint/CDC tools, including setting up flows from scratch.
  • •Knowledge of creating synthesis constraints and Static Timing Analysis (STA); synthesis tool familiarity is a plus.
  • •Experience with simulation tools (e.g., Xcelium, Verisium) and cross-functional communication.
Experience:5+ yearsDigital design
Education:Master's
Skills:CommunicationCross-functional collaborationAutomationProblem-solvingQuality assurance
Tech Stack:VerilogSystemVerilogLint/CDC toolsStatic Timing Analysis (STA)Synthesis constraintsXceliumVerisiumPythonPerlTclAMBAARM IPsPCIeEthernetDDR

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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Glassdoor: 3.9
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