IC Layout Engineer

Execute high-quality IC layouts across standard cells, I/O pads, and mixed-signal IP for advanced process nodes. Manage planning and floorplanning from the transistor level through cell and block execution, while applying design guidelines and process rules to achieve high-performance, robust results. Collaborate across sites, adopt new methodologies, and support physical verification including DRC, LVS, ERC, and antenna checks using Cadence Virtuoso and Calibre.